US Patent 8,618,855 — Semiconductor device, and display device and electronic device having the same

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Abstract

An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Claims

15 · 4 independent · depth 3

15 granted claims

›1.independentA semiconductor device comprising a flip-flop circuit, the flip-flop circuit comprising:na first transistor;a second transistor;a third transistor;a f…+11

A semiconductor device comprising a flip-flop circuit, the flip-flop circuit comprising:na first transistor;a second transistor;a third transistor;a fourth transistor;a fifth transistor;a first wiring;a second wiring;a third wiring; anda fourth wiring,wherein a first terminal of the first transistor is electrically connected to the first wiring, a second terminal of the first transistor is electrically connected to a second terminal of the second transistor, and a gate terminal of the first transistor is directly connected to a gate terminal of the fourth transistor,wherein a first terminal of the second transistor is electrically connected to the second wiring, and a gate terminal of the second transistor is directly connected to a second terminal of the third transistor,wherein a first terminal of the third transistor is electrically connected to the third wiring, and a gate terminal of the third transistor is directly connected to a second terminal of the fourth transistor and a second terminal of the fifth transistor,wherein a first terminal of the fourth transistor is electrically connected to the second wiring,wherein a first terminal of the fifth transistor is electrically connected to the fourth wiring, and a gate terminal of the fifth transistor is electrically connected to the fourth wiring,wherein the gate terminal of the first transistor is electrically connected to a first terminal of a transistor for making the gate terminal of the first transistor into a floating state,wherein a second terminal of the transistor is electrically connected to the third wiring,wherein the first terminal of the third transistor is configured to receive a first signal through the third wiring,wherein the first terminal of the fifth transistor is configured to receive a second signal through the fourth wiring,wherein the first terminal of the first transistor is configured to receive a third signal through the first wiring,wherein the third signal is an inverted signal of the first signal, andwherein the third wiring is not electrically connected to the fourth wiring.

›5.↳ 1multiple · 1, 2, 3, 4The semiconductor device according to any one of claims 1 to 4, wherein a ratio W/L of channel length L to channel width W of the fourth transistor is…d2

›6.↳ 1multiple · 1, 2, 3, 4The semiconductor device according to any one of claims 1 to 4, wherein the first transistor and the third transistor have the same conductivity type.d2

›7.↳ 1multiple · 1, 2, 3, 4The semiconductor device according to any one of claims 1 to 4, wherein the first transistor and the third transistor are n-channel transistors.d2

›8.↳ 1multiple · 1, 2, 3, 4The semiconductor device according to any one of claims 1 to 4, wherein a capacitor which is electrically connected between the second terminal of the…d2+1

›10.↳ 1multiple · 1, 2, 3, 4The semiconductor device according to any one of claims 1 to 4,nwherein a first signal is supplied to the first wiring; andwherein an inverted first s…d2

›11.↳ 1multiple · 1, 2, 3, 4A display device comprising:na driver circuit including the semiconductor device according to any one of claims 1 to 4; anda plurality of pixels,where…d2+3

›15.↳ 1multiple · 1, 2, 3, 4The semiconductor device according to any one of claims 1-4, wherein the first signal is a clock signal and the third signal is an inverted clock sign…d2

›2.independentA semiconductor device comprising a flip-flop circuit, the flip-flop circuit comprising:na first transistor;a second transistor;a third transistor;a f…

A semiconductor device comprising a flip-flop circuit, the flip-flop circuit comprising:na first transistor;a second transistor;a third transistor;a fourth transistor;a fifth transistor;a sixth transistor;a first wiring;a second wiring;a third wiring;a fourth wiring; anda fifth wiring,wherein a first terminal of the first transistor is electrically connected to the first wiring, a second terminal of the first transistor is electrically connected to a second terminal of the second transistor, and a gate terminal of the first transistor is directly connected to a gate terminal of the fourth transistor and a second terminal of the sixth transistor,wherein a first terminal of the second transistor is electrically connected to the second wiring, and a gate terminal of the second transistor is directly connected to a second terminal of the third transistor,wherein a first terminal of the third transistor is electrically connected to the third wiring, and a gate terminal of the third transistor is directly connected to a second terminal of the fourth transistor and a second terminal of the fifth transistor,wherein a first terminal of the fourth transistor is electrically connected to the second wiring,wherein a first terminal of the fifth transistor is electrically connected to the fourth wiring, and a gate terminal of the fifth transistor is electrically connected to the fourth wiring,wherein a first terminal of the sixth transistor is electrically connected to the fourth wiring, and a gate terminal of the sixth transistor is electrically connected to the fifth wiring,wherein the first terminal of the third transistor is configured to receive a first signal through the third wiring,wherein the first terminal of the fifth transistor is configured to receive a second signal through the fourth wiring,wherein the first terminal of the first transistor is configured to receive a third signal through the first wiring,wherein the third signal is an inverted signal of the first signal, andwherein the third wiring is not electrically connected to the fourth wiring.

›3.independentA semiconductor device comprising a flip-flop circuit, the flip-flop circuit comprising:na first transistor;a second transistor;a third transistor;a f…

A semiconductor device comprising a flip-flop circuit, the flip-flop circuit comprising:na first transistor;a second transistor;a third transistor;a fourth transistor;a fifth transistor;a sixth transistor;a seventh transistor;a first wiring;a second wiring;a third wiring;a fourth wiring; anda fifth wiring,wherein a first terminal of the first transistor is electrically connected to the first wiring, a second terminal of the first transistor is electrically connected to a second terminal of the second transistor, and a gate terminal of the first transistor is directly connected to a gate terminal of the fourth transistor, a second terminal of the sixth transistor, and a second terminal of the seventh transistor,wherein a first terminal of the second transistor is electrically connected to the second wiring, and a gate terminal of the second transistor is directly connected to a second terminal of the third transistor and electrically connected to a gate terminal of the seventh transistor,wherein a first terminal of the third transistor is electrically connected to the third wiring, and a gate terminal of the third transistor is directly connected to a second terminal of the fourth transistor and a second terminal of the fifth transistor,wherein a first terminal of the fourth transistor is electrically connected to the second wiring,wherein a first terminal of the fifth transistor is electrically connected to the fourth wiring, and a gate terminal of the fifth transistor is electrically connected to the fourth wiring,wherein a first terminal of the sixth transistor is electrically connected to the fourth wiring, and a gate terminal of the sixth transistor is electrically connected to the fifth wiring,wherein a first terminal of the seventh transistor is electrically connected to the second wiring,wherein the first terminal of the third transistor is configured to receive a first signal through the third wiring,wherein the first terminal of the fifth transistor is configured to receive a second signal through the fourth wiring,wherein the first terminal of the first transistor is configured to receive a third signal through the first wiring,wherein the third signal is an inverted signal of the first signal, andwherein the third wiring is not electrically connected to the fourth wiring.

›4.independentA semiconductor device comprising a flip-flop circuit, the flip-flop circuit comprising:na first transistor;a second transistor;a third transistor;a f…

A semiconductor device comprising a flip-flop circuit, the flip-flop circuit comprising:na first transistor;a second transistor;a third transistor;a fourth transistor;a fifth transistor;a sixth transistor;a seventh transistor;an eighth transistor;a first wiring;a second wiring;a third wiring;a fourth wiring;a fifth wiring; anda sixth wiring,wherein a first terminal of the first transistor is electrically connected to the first wiring, a second terminal of the first transistor is electrically connected to a second terminal of the second transistor, and a gate terminal of the first transistor is directly connected to a gate terminal of the fourth transistor, a second terminal of the sixth transistor, a second terminal of the seventh transistor, and a second terminal of the eighth transistor,wherein a first terminal of the second transistor is electrically connected to the second wiring, and a gate terminal of the second transistor is directly connected to a second terminal of the third transistor and electrically connected to a gate terminal of the seventh transistor,wherein a first terminal of the third transistor is electrically connected to the third wiring, and a gate terminal of the third transistor is directly connected to a second terminal of the fourth transistor and a second terminal of the fifth transistor;wherein a first terminal of the fourth transistor is electrically connected to the second wiring,wherein a first terminal of the fifth transistor is electrically connected to the fourth wiring, and a gate terminal of the fifth transistor is electrically connected to the fourth wiring,wherein a first terminal of the sixth transistor is electrically connected to the fourth wiring, and a gate terminal of the sixth transistor is electrically connected to the fifth wiring,wherein a first terminal of the seventh transistor is electrically connected to the second wiring,wherein a first terminal of the eighth transistor is electrically connected to the second wiring, and a gate terminal of the eighth transistor is electrically connected to the sixth wiring,wherein the first terminal of the third transistor is configured to receive a first signal through the third wiring,wherein the first terminal of the fifth transistor is configured to receive a second signal through the fourth wiring,wherein the first terminal of the first transistor is configured to receive a third signal through the first wiring,wherein the third signal is an inverted signal of the first signal, andwherein the third wiring is not electrically connected to the fourth wiring.

Classifications

14 codes

IPC · International Patent Classification

Section G — Physics

G11C19/00

Section H — Electricity

H03K3/00

USPC · US Patent Classification

327/201327/215327/200377/64327/217327/216327/199327/218327/208327/210377/69327/219

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Jesse Y Miyoshi

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1 priority documents

›Priority documents — 1

Type	Document	Date
related publication	US 20130314139 A1	28 Nov 2013

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