The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The synthesis transform is then made with accurate timing information from the placement, and the process is incrementally iterative toward the final timing enclosure of the design. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic.

Claims

24 · 3 independent · depth 2

24 granted claims

›1.independentA method of designing an integrated circuit (IC), the method comprising:ndetermining a placement decision for a portion of a design of the IC at a hig…+7

›2.↳ 1A method as in claim 1 wherein the high level circuit representation includes at least one component which has not had an implementation, in a chip pr…d2

›3.↳ 1A method as in claim 1 further comprising:nrepeating a synthesis transform for the portion of the high level circuit presentation previously synthesiz…d2

›4.↳ 1A method as in claim 1 further comprising:ndetermining placement decisions while synthesis from the high level circuit description is still to be comp…d2

›5.↳ 1A method as in claim 1 wherein the synthesis transform is one of:nan adder tree decomposition;an and/or gate decomposition;a flattening of the netlist…d2

›6.↳ 1A method as in claim 1 wherein the synthesis transform assembles RTL components compiled from the high level circuit representation.d2

›7.↳ 1A method as in claim 1 wherein the synthesis transform is incremental.d2

›8.↳ 1A method as in claim 1 wherein the synthesis transform is partial synthesis for a few objects for the portion of the circuit design.d2

›9.independentA non-transitory machine readable storage medium containing a plurality of executable instructions, which when executed on a digital processing system…+7

›10.↳ 9A non-transitory machine readable storage medium as in claim 9 wherein the high level circuit representation includes at least one component which has…d2

›11.↳ 9A non-transitory machine readable storage medium as in claim 9 further comprising instructions that cause the system to perform operations comprisingn…d2

›12.↳ 9A non-transitory machine readable storage medium as in claim 9 further comprising instructions that cause the system to perform operations comprisingn…d2

›13.↳ 9A non-transitory machine readable storage medium as in claim 9 wherein the synthesis transform is one of:nan adder tree decomposition;an and/or gate d…d2

›14.↳ 9A non-transitory machine readable storage medium as in claim 9 wherein the synthesis transform assembles RTL components compiled from the high level c…d2

›15.↳ 9A non-transitory machine readable storage medium as in claim 9 wherein the synthesis transform is incremental.d2

›16.↳ 9A non-transitory machine readable storage medium as in claim 9 wherein the synthesis transform is partial synthesis for a few objects for the portion …d2

›17.independentA data processing system to design an integrated circuit (IC), the data processing system comprising:nmeans for determining a placement decision for a…+7

›18.↳ 17A data processing system as in claim 17 wherein the high level circuit representation includes at least one component which has not had an implementat…d2

›19.↳ 17A data processing system as in claim 17 further comprisingnmeans for repeating a synthesis transform for the portion of the high level circuit present…d2

›20.↳ 17A data processing system as in claim 17 further comprising:nmeans for determining placement decisions while synthesis from the high level circuit desc…d2

›21.↳ 17A data processing system as in claim 17 wherein the synthesis transform is one of:nan adder tree decomposition;an and/or gate decomposition;a flatteni…d2

›22.↳ 17A data processing system as in claim 17 wherein the synthesis transform assembles RTL components compiled from the high level circuit representation.d2

›23.↳ 17A data processing system as in claim 17 wherein the synthesis transform is incremental.d2

›24.↳ 17A data processing system as in claim 17 wherein the synthesis transform is partial synthesis for a few objects for the portion of the circuit design.d2

Classifications

6 codes

IPC · International Patent Classification

Section G — Physics

G06F17/50

USPC · US Patent Classification

716/119716/104716/122716/123716/105

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Pendency

5.3 y

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3 RCE

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Jack Chiang

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Priority chain

2 priority documents

Priority

23 Jul 2007

earliest claimed

›Priority documents — 2

Type	Document	Date
provisional	US 60951436	23 Jul 2007
related publication	US 20090031277 A1	29 Jan 2009

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