Polishing estimation/evaluation device, overpolishing condition calculation device, and computer-readable non-transitory medium thereof
Granted 12 Nov 2013 · 2 office actions
Assignee: Fujitsu Limited
Law firm: Law firm · Log in to unlock
Attorney: Attorney · Log in to unlock
Inventors: Daisuke Fukuda · Examiner: Vuthe Siek · AU 2825 · TC 2800
Life of the patent
7 dated eventsAbstract
A polishing estimation/evaluation device includes a dividing unit, an overpolished area extracting unit, and a dummy modifying unit. The dividing unit divides a layout of an integrated circuit into a plurality of partial areas. The overpolished area extracting unit refers to an overpolishing condition indicating whether overpolishing occurs in a vicinity of a partial area based on a wiring density in the partial area and a wiring density in surrounding areas of the partial area, and extracts a partial area where the overpolishing occurs from the plurality of partial areas obtained by the division by the dividing unit. The dummy modifying unit modifies dummy wiring in the partial area where the overpolishing occurs extracted by the overpolished area extracting unit and/or dummy wiring in surrounding areas of the partial area to reduce the number of partial areas where the overpolishing occurs.
Claims
4 · 3 independent · depth 2Classifications
2 codes- G06F17/50
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1 priority documents›Priority documents — 1
| Type | Document | Date |
|---|---|---|
| related publication | US 20120323526 A1 | 20 Dec 2012 |
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