A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.

Claims

22 · 2 independent · depth 3

22 granted claims

›1.independentA semiconductor device, comprising:na substrate including a chip region;a plurality of dielectric films formed on the substrate;seal rings formed in a…+14

›2.↳ 1The semiconductor device of claim 1,nwherein an end of the cap layer located father from the second seal ring is located farther than the first seal r…d2

›3.↳ 1The semiconductor device of claim 1, wherein:nat least part of the first and second seal rings are buried in a recess portion formed in one of the plu…d2

›4.↳ 1The semiconductor device of claim 1,nwherein at least one of the first and second seal rings includes two or more seal vias.d2+1

›5.↳ 1The semiconductor device of claim 1,nwherein the first and second seal rings include at least one material selected from the group consisting of W, Al…d2

›6.↳ 1The semiconductor device of claim 1,nwherein the cap layer includes Al.d2

›7.↳ 1The semiconductor device of claim 1,nwherein the first seal ring is an outermost seal ring out of the seal rings.d2

›8.↳ 1The semiconductor device of claim 1,nwherein the first and second seal rings and the first opening continuously surround the chip region.d2

›9.↳ 1The semiconductor device of claim 1, further comprising:nan interconnect formed in at least one of the plurality of dielectric films in the chip regio…d2+1

›12.↳ 1The semiconductor device of claim 1,nwherein the cap layer covers an entirety of the upper surface of the first seal ring.d2

›13.↳ 1The semiconductor device of claim 1,nwherein the protection film is not in contact with the first seal ring.d2

›14.↳ 1The semiconductor device of claim 1, wherein a width of the cap layer is larger than a width of the first seal ring formed in the first dielectric fil…d2

›15.↳ 1The semiconductor device of claim 1, a length of a portion of the cap layer in contact with an upper surface of the protection film, in a direction pe…d2

›16.independentA semiconductor device, comprising:na substrate including a chip region;a plurality of dielectric films formed on the substrate;seal rings formed in a…+6

›17.↳ 16The semiconductor device of claim 16,nwherein the protection film is in contact with a surface of the interconnect.d2

›18.↳ 16The semiconductor device of claim 16,nwherein an end of the cap layer located father from the second seal ring is located farther than the first seal …d2

›19.↳ 16The semiconductor device of claim 16,nwherein a width of the cap layer is larger than the width of the first opening.d2

›20.↳ 16The semiconductor device of claim 16, wherein a distance from an interface between the cap layer and the first seal ring to the substrate is substanti…d2

›21.↳ 16The semiconductor device of claim 16, wherein a width of the cap layer is larger than a width of the first seal ring formed in the first dielectric fi…d2

›22.↳ 16The semiconductor device of claim 16, a length of a portion of the cap layer in contact with an upper surface of the protection film, in a direction p…d2

Classifications

6 codes

IPC · International Patent Classification

Section H — Electricity

H01L29/66

USPC · US Patent Classification

257/409257/E29.013257/E23.002257/620257/484

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Tu-Tu Ho

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Type	Document	Date
related publication	US 20120280401 A1	8 Nov 2012

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