Manufacturing method for array substrate with fringe field switching type thin film transistor liquid crystal display

The method for manufacturing an array substrate of an FFS type TFT-LCD according to claim 1, wherein the step 1 comprises:nStep 11: depositing the first transparent conductive film and the first metal film on the transparent substrate sequentially;Step 12: applying first photoresist, and performing an exposing and developing process by using a first half tone mask so that a photoresist-totally-remaining region of the first photoresist corresponds to regions of the gate lines, the gate electrodes and the common electrode lines of the array substrate, a photoresist-partially-exposed region corresponds to a region of the common electrodes of the array substrate, and a photoresist-totally-removed region corresponds to the other regions;Step 13: performing a first etching process to remove the first metal film and the first transparent conductive film in the photoresist-totally-removed region and to form patterns including the gate lines, the gate electrodes, the common electrodes and the common electrode lines;Step 14: performing an ashing process with respect to the first photoresist to expose the first metal film in the photoresist-partially-remaining region;Step 15: performing a second etching process to remove the first metal film in the photoresist-partially-remaining region and expose the common electrodes; andStep 16: peeling off the residual first photoresist.

The method for manufacturing an array substrate of an FFS type TFT-LCD according to claim 1, wherein the step 2 comprises:nStep 21: depositing the gate insulating film, the semiconductor film and the impurity-doped semiconductor film on the structure in the step 1;Step 22: applying second photoresist and performing an exposing and developing process by using a second half tone mask so that a photoresist-totally-remaining region of the second photoresist corresponds to a region of the TFT channels, a photoresist-totally-removed region corresponds to a region of the gate lines in the PAD region of the array substrate, and a photoresist-partially-remaining region corresponds to the other regions;Step 23: performing a third etching process to remove the impurity-doped semiconductor film, the semiconductor film and the gate insulating film in the photoresist-totally-removed region, expose the gate lines in the PAD region and form patterns of connection holes of the gate lines in the PAD region and the gate insulating layer;Step 24: performing an ashing process with respect to the second photoresist to expose the impurity-doped semiconductor film in the photoresist-partially-remaining region;Step 25: performing a fourth etching process to remove the impurity-doped semiconductor film, the semiconductor film and the gate insulating film in the photoresist-partially-remaining region and form patterns including the semiconductor layer; andStep 26: peeling off the residual second photoresist.

The method for manufacturing an array substrate of an FFS type TFT-LCD according to claim 1, wherein the step 3 comprises:nStep 31: deposition a second metal film on the structure obtained in the step 2;Step 32: applying third photoresist and performing an exposing and developing process by using a third half tone mask so that a photoresist-totally-removed region of the third photoresist corresponds to a region of the pixel electrodes of the array substrate, a photoresist-partially-remaining region corresponds to regions of the source electrodes, the drain electrodes, the gate lines in the PAD region, the data lines in the PAD region and the common electrode lines in the PAD region, and a photoresist-totally-remaining region corresponds to the other regions;Step 33: performing a fifth etching process to remove the second metal film in the photoresist-totally-removed region;Step 34: performing an ashing process with respect to the third photoresist to expose the second metal film in the photoresist-partially-remaining region;Step 35: deposition a second transparent conductive film;Step 36: performing a lifting-off process to remove the second transparent conductive film on the residual third photoresist and form the pattern of the pixel electrodes; andStep 37: performing a sixth etching process to remove the exposed second metal film and the exposed impurity-doped semiconductor film and form patterns of the source electrodes, the drain electrodes and the TFT channels.

The method for manufacturing an array substrate of an FFS type TFT-LCD according to claim 5, wherein the step 100 comprises:nStep 1100: depositing the first transparent conductive film and the first metal film on the transparent substrate sequentially;Step 1200: applying first photoresist, and performing an exposing and developing process by using a first half tone mask so that a photoresist-totally-remaining region of the first photoresist corresponds to regions of the gate lines, the gate electrodes and the common electrode lines of the array substrate, a photoresist-partially-exposed region corresponds to a region of the pixel electrodes of the array substrate, and a photoresist-totally-removed region corresponds to the other regions;Step 1300: performing a first etching process to remove the first metal film and the first transparent conductive film in the photoresist-totally-removed region and to form patterns including the gate lines, the gate electrodes, the pixel electrodes and the common electrode lines;Step 1400: performing an ashing process with respect to the first photoresist to expose the first metal film in the photoresist-partially-remaining region;Step 1500: performing a second etching process to remove the first metal film in the photoresist-partially-remaining region and expose the pixel electrodes; andStep 1600: peeling off the residual first photoresist.

The method for manufacturing an array substrate of an FFS type TFT-LCD according to claim 5, wherein the step 200 comprises:nStep 2100: depositing the gate insulating film, the semiconductor film and the impurity-doped semiconductor film on the structure in the step 100;Step 2200: applying second photoresist and performing an exposing and developing process by using a second half tone mask so that a photoresist-totally-remaining region of the second photoresist corresponds to a region of the TFT channels, a photoresist-totally-removed region corresponds to a region of the via holes and the gate lines in the PAD region of the array substrate, and a photoresist-partially-remaining region corresponds to the other regions;Step 2300: performing a third etching process to remove the impurity-doped semiconductor film, the semiconductor film and the gate insulating film in the photoresist-totally-removed region, expose a part of the pixel electrodes and the gate lines in the PAD region and form patterns of via holes, the connection holes of the gate lines in the PAD region and the gate insulating layer;Step 2400: performing an ashing process with respect to the second photoresist to expose the impurity-doped semiconductor film in the photoresist-partially-remaining region;Step 2500: performing a fourth etching process to remove the impurity-doped semiconductor film, the semiconductor film and the gate insulating film in the photoresist-partially-remaining region and form patterns including the semiconductor layer; andStep 2600: peeling off the residual second photoresist.

The method for manufacturing an array substrate of an FFS type TFT-LCD according to claim 5, wherein the step 300 comprises:nStep 3100: deposition a second metal film on the structure obtained in the step 200;Step 3200: applying third photoresist and performing an exposing and developing process by using a third half tone mask so that a photoresist-totally-removed region of the third photoresist corresponds to a region of the common electrodes of the array substrate, a photoresist-partially-remaining region corresponds to regions of the source electrodes, the drain electrodes, the gate lines in the PAD region, the data lines in the PAD region and the common electrode lines in the PAD region, and a photoresist-totally-remaining region corresponds to the other regions;Step 3300: performing a fifth etching process to remove the second metal film in the photoresist-totally-removed region;Step 3400: performing an ashing process with respect to third the photoresist to expose the second metal film in the photoresist-partially-remaining region;Step 3500: deposition a second transparent conductive film;Step 3600: performing a lifting-off process to remove the second transparent conductive film on the residual third photoresist and form patterns of the common electrodes and connection lines for connecting the drain electrodes and the pixel electrodes; andStep 3700: performing a sixth etching process to remove the exposed second metal film and the exposed impurity-doped semiconductor film and form patterns including the source electrodes, the drain electrodes and the TFT channels.