Signal processing apparatus, signal transmitting system, and signal processing method

A signal processing apparatus executing a decoding process for a digital signal Manchester-encoded by assigning two bits of “10†to any one of binary digital signals “0 and “1†, and assigning two bits of “01†to the other binary digital signal, comprising:na decoding unit executing the decoding process with a processing unit corresponding to a term of two bits of the Manchester-encoded digital signal so as to detect only any one of a first bit and a second bit of the Manchester-encoded digital signal,wherein the decoding unit detects only the second bit of the Manchester-encoded digital signal at a falling edge or a rising edge of a clock switched by the first bit and the second bit of the Manchester-encoded digital signal.

A signal processing apparatus executing a decoding process for a digital signal Manchester-encoded by assigning two bits of “10†to any one of binary digital signals “0 and “1†, and assigning two bits of “01†to the other binary digital signal, comprising:na decoding unit executing the decoding process with a processing unit corresponding to a term of two bits of the Manchester-encoded digital signal so as to detect only any one of a first bit and a second bit of the Manchester-encoded digital signal,wherein the decoding unit executes the decoding process for the Manchester-encoded digital signal by using only a circuit element operating as substantially phase-synchronized with a switching timing of the first bit and the second bit of the Manchester-encoded digital signal.

A signal processing apparatus executing a decoding process for a digital signal Manchester-encoded by assigning two bits of “10†to any one of binary digital signals “0 and “1†, and assigning two bits of “01†to the other binary digital signal, comprising:na decoding unit executing the decoding process with a processing unit corresponding to a term of two bits of the Manchester-encoded digital signal so as to detect only any one of a first bit and a second bit of the Manchester-encoded digital signal;a clock generating circuit generating a clock synchronized with a phase of the Manchester-encoded digital signal from the corresponding Manchester-encoded digital signal; anda binarizing circuit binarizing the Manchester-encoded digital signal to output the binarized Manchester-encoded digital signal to the decoding unit and the clock generating circuit,wherein the decoding unit extracts only the second bit of the Manchester-encoded digital signal output from the binarizing circuit at the falling edge or the rising edge of the clock output from the clock generating circuit.

A signal transmitting system, comprising:na transmitting unit including a Manchester-encoding unit generating a digital signal Manchester-encoded by assigning two hits of “10†to any one of binary digital signals “0 and “1†of transmission data to be transmitted, and assigning two bits of “01†to the other binary digital signal; anda receiving unit including a decoding unit executing a decoding process for the Manchester-encoded digital signal with a processing unit corresponding to a term of two bits of the Manchester-encoded digital signal so as to detect only any one of a first bit and a second bit of the Manchester-encoded digital,wherein the decoding unit executes the decoding process for the Manchester-encoded digital signal by using only a circuit element operating as substantially phase-synchronized with a switching timing of the first bit and the second bit of the Manchester-encoded digital signal.

A signal processing method for a digital signal Manchester-encoded by assigning two bits of “10†to any one of binary digital signals “0 and “1†, and assigning two bits of “01†to the other binary digital signal, comprising:na decoding step of executing a decoding process with a processing unit corresponding to a term of two bits of the Manchester-encoded digital signal so as to detect only any one of a first bit and a second bit of the Manchester-encoded digital signal; anda clock generating step of generating a clock phase-synchronized with the Manchester-encoded digital signal, whereinthe decoding step extracts only the second bit of the Manchester-encoded digital signal at a falling edge or a rising edge of the clock generated by the clock generating step.