Regulator circuit and RFID tag including the same in wireless communication to improve noise margin

A regulator circuit comprising:na first terminal supplied with a first potential;a second terminal having a second potential, wherein the first potential is different from the second potential;a bias circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a resistor, and a bypass capacitor; anda voltage regulator electrically connected to the first terminal, the second terminal, and the bias circuit,wherein a gate of the first transistor is electrically connected to a gate of the second transistor, one of a source and a drain of the first transistor is electrically connected to the second terminal, and the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,wherein the gate of the second transistor is electrically connected to one of a source and a drain of the second transistor, and one of a source and a drain of the fourth transistor, and the other of the source and the drain of the second transistor is electrically connected to the second terminal,wherein a gate of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor, and the other of the source and the drain of the third transistor is electrically connected to the first terminal,wherein a gate of the fourth transistor is electrically connected to the one of the source and the drain of the third transistor,wherein one terminal of the resistor is electrically connected to the gate of the third transistor, and the other terminal of the resistor is electrically connected to the first terminal, andwherein the bypass capacitor is provided between a node connected to the gate of the fourth transistor and one of the first terminal and the second terminal.

A regulator circuit comprising:na first terminal supplied with a first potential;a second terminal having a second potential, wherein the first potential is different from the second potential;a bias circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a resistor, and a bypass capacitor; anda voltage regulator electrically connected to the first terminal, the second terminal, and the bias circuit,wherein a gate of the first transistor is electrically connected to a gate of the second transistor, one of a source and a drain of the first transistor is electrically connected to the second terminal, and the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,wherein the gate of the second transistor is electrically connected to one of a source and a drain of the second transistor, and one of a source and a drain of the fourth transistor, and the other of the source and the drain of the second transistor is electrically connected to the second terminal,wherein a gate of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor, and the other of the source and the drain of the third transistor is electrically connected to the first terminal,wherein a gate of the fourth transistor is electrically connected to the one of the source and the drain of the third transistor,wherein one terminal of the resistor is electrically connected to the gate of the third transistor, and the other terminal of the resistor is electrically connected to the first terminal, andwherein the bypass capacitor is provided between a node connected to the gate of the first transistor and one of the first terminal and the second terminal.

A regulator circuit comprising:na first terminal supplied with a first potential;a second terminal having a second potential, wherein the first potential is different from the second potential;a bias circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a resistor, and a bypass capacitor; anda voltage regulator electrically connected to the first terminal, the second terminal, and the bias circuit,wherein a gate of the first transistor is electrically connected to a gate of the second transistor, one of a source and a drain of the first transistor is electrically connected to the second terminal, and the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,wherein the gate of the second transistor is electrically connected to one of a source and a drain of the second transistor, and one of a source and a drain of the fourth transistor, and the other of the source and the drain of the second transistor is electrically connected to the second terminal,wherein a gate of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor, and the other of the source and the drain of the third transistor is electrically connected to the first terminal,wherein a gate of the fourth transistor is electrically connected to the one of the source and the drain of the third transistor,wherein one terminal of the resistor is electrically connected to the gate of the third transistor, and the other terminal of the resistor is electrically connected to the first terminal, andwherein the bypass capacitor is provided between a node connected to the gate of the third transistor and one of the first terminal and the second terminal.

A regulator circuit comprising:na first terminal supplied with a first potential;a second terminal having a second potential, wherein the first potential is different from the second potential;a bias circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a resistor, a first bypass capacitor, a second bypass capacitor, and a third bypass capacitor; anda voltage regulator electrically connected to the first terminal, the second terminal, and the bias circuit,wherein a gate of the first transistor is electrically connected to a gate of the second transistor, one of a source and a drain of the first transistor is electrically connected to the second terminal, and the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,wherein the gate of the second transistor is electrically connected to one of a source and a drain of the second transistor, and one of a source and a drain of the fourth transistor, and the other of the source and the drain of the second transistor is electrically connected to the second terminal,wherein a gate of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor, and the other of the source and the drain of the third transistor is electrically connected to the first terminal,wherein a gate of the fourth transistor is electrically connected to the one of the source and the drain of the third transistor,wherein one terminal of the resistor is electrically connected to the gate of the third transistor, and the other terminal of the resistor is electrically connected to the first terminal, wherein the first bypass capacitor is provided between a node connected to the gate of the fourth transistor and one of the first terminal and the second terminal,wherein the second bypass capacitor is provided between a node connected to the gate of the first transistor and one of the first terminal and the second terminal, andwherein the third bypass capacitor is provided between a node connected to the gate of the third transistor and one of the first terminal and the second terminal.

A semiconductor device comprising:na semiconductor integrated circuit including a regulator circuit;a support provided at least over a surface of the semiconductor integrated circuit; anda shield provided at least over the surface of the semiconductor integrated circuit with the support interposed therebetween,wherein the regulator circuit comprises:a first terminal supplied with a first potential;a second terminal having a second potential, wherein the first potential is different from the second potential;a bias circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a resistor, and at least one bypass capacitor; anda voltage regulator electrically connected to the first terminal, the second terminal, and the bias circuit,wherein a gate of the first transistor is electrically connected to a gate of the second transistor, one of a source and a drain of the first transistor is electrically connected to the second terminal, and the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor,wherein one of a source and a drain of the second transistor is electrically connected to the second terminal, the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor, the gate of the second transistor is electrically connected to the other of the source and the drain of the second transistor,wherein a gate of the third transistor is electrically connected to the other of the source and the drain of the fourth transistor, and the other of the source and the drain of the third transistor is electrically connected to the first terminal,wherein a gate of the fourth transistor is electrically connected to the one of the source and the drain of the third transistor,wherein one terminal of the resistor is electrically connected to the gate of the third transistor, and the other terminal of the resistor is electrically connected to the first terminal, andwherein a bypass capacitor is provided between a node connected to at least one of gates of the first transistor, the second transistor, the third transistor, and the fourth transistor and one of the first terminal and the second terminal.