CMOS bandgap reference source circuit with low flicker noises

1. Field of Invention

The present invention relates to the field of analog integrated circuits and mixed signals integrated circuits, particularly, to a CMOS bandgap reference source circuit with low flicker noises.

2. Brief Description of Related Arts

Bandgap reference source circuit is an important part of the analog integrated circuit and is widely applied to various analog and mixed signal integrated circuits, such as switching power supply (DC-DC), linear regulator, digital-analog converting circuits (ADC&DAC) and so on, which all need a reference voltage without changing along with the power supply and temperature. Among various reference circuits, the bandgap reference source circuit has better temperature characteristic and power supply rejection ratio (PSRR), is not subject to manufacturing techniques, and accordingly becomes the first option for designing the reference circuit.

For some system circuits requiring a reference voltage with high accuracy, a CMOS bandgap reference source circuit with low noises is necessary. Two main noise sources with the CMOS bandgap reference result from the flicker noises of field effect transistors (FET) and thermo-noise of all components in circuits. Generally speaking, the flicker noises of FET is inversely proportional to the frequency. When the frequency is about dozens of KHz, the flicker noise becomes the main noise source of the CMOS bandgap reference circuit. Consequently, bigger flicker noises have limited the application of the CMOS bandgap reference circuit. For example, the high performance audio DAC circuit working at the range of 20 Hz to 20 KHz really needs a low noise reference circuit to ensure the performance of the converting circuit.

FIG. 1 shows a conventional CMOS bandgap reference source circuit with the following operational principle. The circuit adopts the feedback control of the operational amplifier to make the voltage of node N 1 and N 2 the same value, thereby the current flowing through resistor R 1 is equal to ΔV be /R 1 , where ΔV be is the difference of V be0 minus V be1 . FET MP 1 , MP 2 and MP 3 compose a current mirror. Since the gate-source voltages of the three FET are the same and three of them all work at saturation regions, their drain-source currents are approximately the same. Therefore, the output of the reference circuit is

V ref = V be ⁢ ⁢ 2 + R 2 R 1 ⁢ Δ ⁢ ⁢ V be .

In the equation, V be2 is negative temperature coefficient and ΔV be is positive coefficient, so that the output voltage with a zero temperature coefficient can be attained by setting up the ratio of R 2 and R 1 .

For the CMOS bandgap reference source circuit shown in FIG. 1 , when operating at the audio range, the two input transistors MP 8 and MP 9 generate flicker noises that become the main noise source. There are a couple of conventional ways to reduce the flicker noises.

(1) increase components area to reduce flicker noises

According to the definition for flicker noises, the noise density of flicker noises is given by the following formula:

V n 2 = K C ox * W * L * 1 f ,

wherein K is a constant with the order of magnitude of 10 −25 V 2 F, not subject to manufacturing techniques; Cox is capacitance of gate oxide per unit area; f is operating frequency; W is the width of FET; L is the length of FET. It can be seen from the formula that flicker noise is inversely proportional to frequency. The smaller the frequency, the bigger the noises. In addition, flicker noise is proportional to the area (W*L) of the FET, therefore, the easiest way to reduce flicker noise is just to expand the area of components. However, this way has led to bigger chips areas, especially when a system requires a reference voltage with lower flicker noises. For instance, suppose there is a ADC with SNR of 100 dB and the voltage of output signals is 1V. To achieve 100 dB SNR, the total maximum noise is 10 uV; therefore, the noise resulting from reference source must be less than 10 uV. To generate that little noise, each of components in the circuit has to expand their areas close to one thousand of square micron.

(2) utilize CHOP structure to average flicker noises

CHOP structure is used to make the flicker noise be equivalent to an offset voltage of a reference circuit, to switch periodically two input terminals and two output terminals of the operational amplifier, to average the power spectrum of the flicker noises in a certain frequency range, and then to achieve a reference voltage output with lower noises through a lowpass filter. However, because the lowpass filter is implemented through resistors and capacitors inside of the chips, it would also cause bigger chips area.

(3) by way of special manufacturing techniques

U.S. Pat. No. 6,514,825, U.S. Pat. No. 6,160,274, U.S. Pat. No. 6,653,679 all use special manufacturing techniques to manufacture FET with low flicker noise. Nevertheless, these methods are relatively complicated, don't fit the mainstream standard of CMOS technology and have increased manufacturing cost as well.

The object of the present invention is to furnish a CMOS bandgap reference source circuit with low flicker noise, which uses two overlapping clocks to control the gate of the input FETs of the operational amplifier of the reference circuit, makes the FETs switch alternately between their strong inversion and cut-off regions; consequently, it can effectively reduce the flicker noises resulting from the FETS, cut down the cost, and dispense with special manufacturing techniques.

According to embodiments of the present invention, the CMOS bandgap reference source circuit with low flicker noises comprises a startup circuit; power-off control circuit; an operational amplifier and a reference voltage generating circuit. The startup circuit is for preventing the reference circuit from working in the erroneous zero currents status; the power-off control circuit is to control whether or not each of branch currents is turned off; the operational amplifier is for adjusting the voltage which is generated from the reference voltage generating circuit and raising the power supply rejection ratio of reference circuit; the reference voltage generating circuit is for outputing final reference voltage.

Various implementations may include one or more of the following advantages. For example, both the positive and the negative input terminal of the operational amplifier are consisting of two same field effect transistors, and both are provided with an input control switch. By controlling the input control switch, the two FETs in the positive input terminal and two FETs in the negative input terminal work alternately between their strong inversion and cut-off regions, whereby FETs generate very little flicker noises, in turn, the flicker noises resulting from two sets of input transistors of the operational amplifier are reduced drastically.

These and other objectives, features, and advantages of the present invention will become apparent from the following detailed description, the accompanying drawings, and the appended claims.

FIG. 1 shows a conventional bandgap reference circuit;

FIG. 2 is a circuit diagram of the present invention;

FIG. 3 shows a comparison diagram of simulated noise waveform of the present invention and the conventional one;

FIG. 4 is an electric schematic diagram of two-phase overlapping clock generating circuit;

FIG. 5 shows a simulated noise waveform diagram of the two-phase overlapping clock generating circuit

Referring to FIG. 2 , a CMOS bandgap reference source circuit with low flicker noises of the present invention comprises a startup circuit, a power-off control circuit, an operational amplifier and a reference voltage generating circuit.

Both the positive and the negative input terminal of the operational amplifier are consisting of two same field effect transistors and both are provided with an input controlled switch. By controlling the input controlled switch, the two FETs in the positive input terminal and two FETs in the negative input terminal work alternately between their strong inversion and cut-off regions, whereby FETs generate very little flicker noises, in turn, the flicker noises resulting from two sets of input transistors of the operational amplifier are reduced drastically.

Said startup circuit comprises of five field effect transistors MP 12 , MP 14 , MN 5 , MN 6 and MN 7 , wherein the width/length ratio of MN 6 is far bigger than MN 12 's. The sources of MP 12 and MP 14 are connected with power supply; the gate of MP 12 is connected with power-off signal PD; the drain of MP 12 , the gate of MN 5 and the drain of MN 6 are connected together; the drain of MP 14 , the drain of MN 7 , the gate of MN 7 are connected with the gate of MN 6 ; the source of MN 5 , the source of MN 6 and the source of MN 7 are all grounded.

The operating principle of the startup circuit is as follows: when the power supply is turned on, the gate of MP 12 is a low level, which means that MP 12 is turned on, therefore, the gate voltage of MN 5 follows the power voltage. When the power voltage is more than the turn-on voltage of MN 5 , then MN 5 is turned on, and the bias voltage of the current mirror in the reference circuit is drawn down to low lever, so that each branch of the circuit has currents flowing through, and the circuit gets into a normal working status from the zero current error status. Once getting into normal working, MN 6 is able to obtain currents through the mirro-image relation with MN 7 ; also because MN 6 is designed with much bigger width/length ratio than MP 12 , the gate of MN 5 is drawn down by MN 6 to low level; finally, the startup process is finished.

Said power-off control circuit comprises of five field effect transistors, MP 11 , MP 13 , MN 8 , MN 9 and MN 10 . When power-off signal PD is a high level, the power-off control circuit turns off every branch current of the reference circuit, so that there is no any power consumption. The gates of MN 9 , MN 10 and MP 13 are connected with power-off signal PD; the drains of MP 13 and MN 8 connected with the gate of MP 11 ; the sources of MP 11 and MP 13 are connected with the power supply; the drain of MP 11 is connected with the drain of MN 5 ; the sources of MN 8 , MN 9 and MN 10 are grounded; the drain of MN 10 is connected with the gate of MN 5 ; the drain of MN 9 is connected with the gate of MN 7 .

Said power-off control circuit is controlled by power-off signal PD. Its operating principle is as follows: when PD is a high level, the gate of MP 11 is a low level, so the offset voltage of the current mirror of the reference circuit is raised by MP 11 to a high level, and in turn all branch currents in the reference circuit are shut down; when PD is a low level, MP 11 is turned off, and the reference circuit is in a normal working state.

The operational amplifier comprises of eleven field effect transistors, MN 1 , MN 2 , MN 3 , MN 4 , MP 4 , MP 5 , MP 6 , MP 7 , MP 8 , MP 9 and MP 10 . MP 7 and MP 8 constitute the negative input terminal of the amplifier; MP 9 and MP 10 constitute the positive input terminal of the amplifier; MP 4 operates as the current source of the amplifier; MN 1 , MN 2 , MN 3 , MN 4 , MN 5 and MN 6 constitute the load output of the current mirror of the amplifier to supply outputs to the amplifier. The sources of MP 4 , MP 5 and MP 6 are connected with a power supply; the gate of MP 4 is connected with the drain of MN 5 ; the drain of MP 4 and the sources of MP 7 , MP 8 , MP 9 and MP 10 are connected together; the drain of MN 4 , the gate of MP 5 , the drain of MP 5 and the gate of MP 6 are connected together; the sources of MN 4 , MN 3 , MN 2 and MN 1 are grounded; the source of MN 4 , the source of MN 3 , the drain of MN 3 , the drain of MP 7 and the drain of MP 8 are connected together; the drains of MP 9 , MP 10 , MN 2 and the gates of MN 2 and MN 1 are connected together; the drain of MN 1 is connected with the drain of MP 6 .

A voltage controlled switch can be used as the input controlled switch of the operational amplifier, such as P-type or N-type EFT. Current controlled switches can also be employed, such as bipolar transistors.

Specifically, the input controlled switch of the amplifier comprises of eight switches SW 1 , SW 2 , SW 3 , SW 4 , SW 5 , SW 6 , SW 7 and SW 8 , which are able to control the working state of the input FETs of the amplifier. The two terminals of SW 1 are respectively connected with the gate of MP 7 and the power supply; the two terminals of SW 2 are respectively connected with the gate of MP 7 and the drain of MP 2 ; the two terminals of SW 3 are respectively connected with the gate of MP 8 and the power supply; the two terminals of SW 4 are respectively connect with the gate of MP 8 and the drain of MP 2 ; the two terminals of SW 5 are respectively connected with the gate of MP 9 and the power supply; the two terminals of SW 6 are respectively connected with the gate of MP 9 and the drain of MP 1 ; the two terminals of SW 7 are respectively connected with the gate of MP 10 and the power supply; the two terminals of SW 8 are respectively connected with the gate of MP 10 and the drain of MP 1 .

All of input controlled switches are connected with two-phase overlapping clock controlled signals, “PH 1 and PH 2 ” as well as “PH 1 N and PH 2 N”, wherein PH 1 N is the phase reversal of PH 1 and PH 2 N is the phase reversal of PH 2 ; PH 1 , PH 1 N, PH 2 and PH 2 N is alternately connected to the input controlled switch.

Said signal PH 2 N is connected to switch SW 1 ; signal PH 2 is connected to switch SW 2 ; Signal PH 1 N is connected to switch SW 3 ; signal PH 1 is connected to switch SW 4 ; Signal PH 1 is connected to switch SW 6 ; signal PH 2 N is connected to switch SW 7 ; signal PH 2 is connected to switch SW 8 .

When PH 1 is a low level and PH 2 is a high level, MP 8 and MP 9 , as the input FETs of the amplifier, work at their strong inversion region, whereas MP 7 and MP 10 work at their cut-off region, with their gates connected with the power supply. When PH 1 is a high level and PH 2 is a low level, MP 7 and MP 10 work at their strong inversion region, whereas MP 8 and MP 9 work at their cut-off region, with their gates connected with the power supply. Consequently, MP 7 , MP 8 , MP 9 and MP 10 work periodically between their strong inversion and cut-off region, which makes FET generate little flicker noises.

Said reference voltage generating circuit comprises of resistors, R 1 and R 2 , field effect transistors, MP 1 , MP 2 and MP 3 , as well as bipolar transistors, Q 0 , Q 1 and Q 2 , thereby generating a reference voltage output irrelevant to temperature and power supply. MP 1 , MP 2 and MP 3 constitute a current mirror, with their sources connected to a power supply; the gates of MP 1 , MP 2 and MP 3 are connected with the drain of MP 6 ; the two terminals of resistor R 1 are respectively connected with the drain of MP 1 and the emitter of bipolar transistor Q 1 ; the drain of MP 2 and the emitter of Q 0 are connected together; the two terminals of resistor R 2 are respectively connected with the drain of MP 3 and the emitter of bipolar transistor Q 3 ; the base and collector of bipolar transistor Q 0 , the base and collector of Q 1 as well as the collector and base of Q 2 are all grounded.

The operating principle of said reference voltage generating circuit is as follows: when the drain voltages of MP 1 and MP 2 become the same by way of the feedback control of said amplifier, currents flowing through resistor R 1 will be ΔV be /R 1 , wherein ΔV be =V be0 −V be1 ; since the gate-source voltages of MP 1 , MP 2 and MP 3 are the same and the three FETs all work at their saturation region, their drain currents are approximately the same, therefore the output of the reference circuit is

V ref = V be ⁢ ⁢ 2 + R 2 R 1 ⁢ Δ ⁢ ⁢ V be

wherein V be2 is negative temperature coefficient, ΔV be is positive temperature coefficient, and correspondingly it can be done to obtain the output voltage under a zero temperature coefficient by determining the ratio of R 2 to R 1 .

As shown in FIG. 3 , curve A represents the simulated noise waveform of the present invention, and curve B represents the conventional one's, both having the same area of FET.

FIG. 4 illustrates how to prevent MP 7 , MP 8 , MP 9 , MP 10 from working simultaneously in their cut-off region, in other words, when switch SW 2 is off, SW 4 is still not on. In addition, because two inputs of the operational amplifier are connected with the power supply, open-loop is caused in the entire reference circuit and this further gives rise to reference voltage jump. To solve the problem, FIG. 4 has overlapped the two-phase clock in FIG. 2 and has formed a overlapping clock generating circuit, wherein two groups of FETs, MP 7 and MP 8 as well as MP 9 and MP 10 , all have a short period of time working in their strong inversion region, so that the reference voltage jump is avoided.

FIG. 5 shows a simulation waveform of a two-phase overlapping clock generating circuit. As seen in the waveform, PH 1 and PH 2 have some time being simultaneously at a high level status, but never being at a low level status at the same time, which makes the two group of FETs, MP 7 and MP 8 as well as MP 9 and MP 10 , have some time being turned on simultaneously, but never being turned off simultaneously, which is for meeting the design demand.

One skilled in the art will understand that the embodiments of the present invention as shown in the drawings and described above is exemplary only and not intended to be limiting.

It will thus be seen that the objects of the present invention have been fully and effectively accomplished. Its embodiments have been shown and described for the purpose of illustrating the functional and structural principles of the present invention and is subject to change without departure from such principles. Therefore, this invention includes all modifications encompassed within the spirit and scope of the following claims.