Method and apparatus for driving a switch

This application claims priority from the following United States provisional patent application, which is hereby incorporated herein by reference in its entirety:

Application No. 60/871,619 filed on Dec. 22, 2006.

The invention generally relates to switches and, more particularly, the invention relates to controlling switches.

Electronic devices often use electronic switches to selectively connect two portions of a circuit. One type of switch has a movable arm that alternatively touches an electrically conductive port (often referred to as a “contact”) on a stationary surface. The arm typically moves in response to a drive signal that forces the arm toward the contact.

To operate with higher speed circuitry, it generally is desirable for a switch to make this connection with its contact in the shortest amount of time. Accordingly, many switches use a relatively high level signal that forces this connection with the contact in the shortest amount of time. For example, the drive signal may rise at a very rapid rate to a maximum voltage to electrostatically urge a micro electromechanical (“MEMS”) cantilever arm toward the stationary contact. This rapid rate undesirably can cause the arm to physically bounce off the contact and oscillate before making a stationary contact.

In response to this, one skilled in the art may produce a lower intensity signal; e.g., one that rises slower. Although it may mitigate the bouncing problem, such a solution undesirably reduces the speed of closing the switch.

In accordance with one embodiment, a method of driving a switch having a movable member and a contact first applies (to the switch) a first signal having a first level, and then applies a second signal having a second level to the switch (after applying the first signal). The first and second levels are the rate of change of the respective signals. The first level is greater than the second level. One or both of the first and second signals cause the movable member to move to electrically connect with the contact.

A method of driving a switch having a movable member may apply one or more signals simultaneously, in sequence, or for an overlapping time. In one embodiment, the one or more signals may be voltage signals. In one embodiment, the one or more signals may be current signals.

In accordance with one embodiment, a drive signal may be produced by a circuit that supplies a voltage or an electrical current to the switch. In one embodiment, a voltage output circuit applies a voltage signal to the switch that has a first level at a first time, and a voltage signal that has a second level after applying the first voltage signal, the first and second levels are the rate of change of the respective voltage signals.

In one embodiment, a current output circuit comprises a current mirror with a current input connected to at least one current source, and a current output connected to the switch. The output of the current mirror serves as a current source to provide charging current to the switch. The current output circuit provides to the switch a first signal of charging current having a first level, and then provides a second signal of charging current having a second level after applying the first signal of charging current.

The movable member illustratively moves to electrically connect with the contact when subjected to a threshold amplitude value. Accordingly, in illustrative embodiments, the first signal has a maximum amplitude that is less than the threshold amplitude value, while the second signal has a maximum amplitude that is greater than the threshold amplitude value.

The method may operate with different types of signals. For example, the first level may be a first voltage, while the second level may be a second voltage. Among other things, the first level and second level may be the rate of increase in voltage relative to time. When executed, the method causes the movable member to move in a manner that causes it to be substantially free of oscillations after electrically contacting the contact.

The signals may be provided a number of different ways. For example, a single source may provide the first and second signals. In other embodiments, a first source provides the first signal and a second source provides the second signal. In yet other embodiments, a first and second source provide one or both of the first and second signals.

In accordance with another embodiment of the invention, a switch driver circuit has a source for delivering a signal having more than one level. Specifically, the signal has a first level, and a second level that is greater than the first level. The switch driver also has an output for delivering the signal so that the signal attains the second level after it has attained the first level.

Among other things, the source may be a plurality of sources or a single source.

Those skilled in the art should more fully appreciate advantages of various embodiments of the invention from the following “Description of Illustrative Embodiments,” discussed with reference to the drawings summarized immediately below.

FIG. 1 schematically shows a MEMS switch in the open position.

FIG. 2 schematically shows a MEMS switch in the closed position.

FIG. 3( a ), FIG. 3( b ) and FIG. 3( c ) schematically show graphs comparing switch reaction to various drive signals.

FIG. 4 is a graph of simulated drive signals.

FIG. 5 is a schematic diagram of an illustrative embodiment of a circuit to drive the switch, including two digital sub-circuits.

FIG. 6( a ) is a schematic of a digital circuit for creating certain control signals.

FIG. 6( b ) is a timing diagram for certain signals of the circuit in FIG. 6( a ).

FIG. 7 is a schematic of a digital circuit for creating a pulsed signal.

FIG. 8 is a schematic of the circuit in FIG. 5 showing certain features in a first operating state.

FIG. 9 is a schematic of the circuit in FIG. 5 showing certain features in a transitional state.

FIG. 10 is a schematic of the circuit in FIG. 5 showing certain features in a second operating state.

FIG. 11 is a schematic diagram of an illustrative embodiment of a circuit to drive the switch.

In illustrative embodiments, a driver applies a drive signal to a switch in a manner that substantially mitigates oscillations while, at the same time, optimizing switch-closing time. To that end, the driver first applies a first signal having a relatively high level to the switch. Before the switch closes, however, the driver applies a second signal having a lower level than that of the first signal. Among other things, the levels may be the rate of change of the signals (e.g., the rate of change of an input voltage). Details of illustrative embodiments are discussed below.

It should be noted that specific details of the switch and certain details of the driver are for illustrative purposes only. Accordingly, discussion of these details are not intended to limit the scope of various embodiments. For example, the switch may have a non-cantilevered arm, or may be formed from non-MEMS processes.

FIG. 1 schematically shows a MEMS switch 100 according to one embodiment of this invention. The switch 100 is in the open position and has a cantilevered arm 105 for alternately making physical contact with a stationary conductor 104 which is electrically connected to a drain electrode 103 . In the open position, no signal will flow from the source electrode 101 to the drain electrode 103 . In this embodiment, the switch 100 is a conventional MEMS switch. In addition, the switch 100 has a stationary substrate 106 that, in addition to supporting the arm 105 , also supports a gate electrode 102 that forms a variable capacitor with the arm 105 . A driver (not shown in FIG. 1 ) is in electrical contact with the gate 102 , and controls the forces applied by the variable capacitor to control arm movement.

FIG. 2 schematically shows the switch 100 of FIG. 1 in the closed position. In the closed position, the arm 105 has moved into contact with the stationary conductor 104 that is electrically connected to a drain electrode 103 . In the closed position, an electrical signal may flow from the source electrode 101 to the drain electrode 103 through the arm 105 .

During operation, a driver (not shown in FIG. 2 ) is in electrical contact with the gate electrode 102 , and applies a drive signal (the driver output) to the gate electrode 102 to selectively urge the cantilevered arm 105 into physical contact with the stationary conductor 104 , thus closing a larger circuit (not shown in FIG. 2 ). Preferably the drive signal rises quickly enough to move the arm 105 in the shortest time, but without causing the switch 100 to bounce. Also preferably, the final level of the drive signal is sufficient to hold the arm 105 securely in the down (i.e., switch closed) position.

FIGS. 3( a ), 3 ( b ) and 3 ( c ) show illustrative responses of an open switch 100 to various drive signals. In the upper illustration of FIG. 3( a ), the driver output causes a fast rising voltage on the gate electrode 102 . As the voltage rises, the arm 105 begins to move downward to close the switch 100 , and ultimately makes contact with the stationary conductor 104 when the voltage reaches the threshold voltage (Vth). However, under this fast-rise approach the tip of the arm 105 makes contact with the stationary conductor 104 at a speed that causes the arm 105 to undesirably bounce, as shown by the oscillations in the lower illustration of FIG. 3( a ). As the drive signal increases towards its final level (80V), the force on the arm 105 is eventually strong enough to hold the arm 105 securely in the down position (i.e., switch closed).

One approach to avoiding the bounce is to ramp the drive signal more gradually. In the upper illustration of FIG. 3( b ), the driver output causes a more slowly rising voltage on the gate electrode 102 . Again, as the applied voltage rises, the arm 105 begins to move downward to close the switch 100 , and when the voltage reaches the threshold voltage (Vth), the arm 105 makes contact with the stationary conductor 104 . Advantageously, the arm 105 does not bounce, as shown in the lower illustration of FIG. 3( b ). Disadvantageously however, the time between application of the drive signal and the closing of the switch 100 in this slow-rise approach is much longer than in the fast-rise approach.

A second approach to avoiding the bounce is to ramp the drive signal at varying rates. For example, the first rate might rise rapidly towards the threshold voltage to get the arm 105 moving in a short time, but then change its rate to rise more slowly so that the final speed of the arm 105 in this approach is less than the final speed of the arm 105 in the fast-rise approach. This third approach closes the switch 100 more quickly than in the slow-rise approach, while at the same time avoiding the oscillations of the fast-rise approach. This approach is shown in the upper illustration of FIG. 3( c ), where the gate voltage rises rapidly toward the threshold voltage, but then the rise of the gate voltage slows. Advantageously, the arm 105 does not bounce, as shown in the lower illustration of FIG. 3( c ), but the switch 100 also closes faster than in the slow-rise approach. After this change of rate, the drive signal continues to rise to a final level, where the force exerted on the arm 105 is sufficient to hold the arm 105 securely in the down position (i.e., switch closed).

In accordance with illustrative embodiments, this drive signal is controlled to prevent the arm 105 from striking the stationary conductor 104 so hard that it will bounce upwardly after making initial contact, and yet to close the switch 100 relatively quickly. As illustrated above, striking the stationary conductor 104 with too much force can cause the arm 105 to oscillate in and out of physical contact with the stationary conductor 104 . Of course, if it is not in physical contact with the stationary conductor 104 , then the arm 105 is not in electrical contact with the stationary conductor 104 . Accordingly, oscillations effectively delay the electrical contact of the arm 105 and stationary conductor 104 . In addition, such oscillations may cause undesirable distortion to a signal passing through the switch 100 , and may also reduce the reliability of the switch 100 .

It should be noted that in addition to being considered a single, multi-level signal, these drive signal signals may also be considered to be multiple, independent signals.

FIG. 4 schematically shows a graphical view of various illustrative drive signal waveforms under different conditions when used with the circuit 500 shown in FIG. 5 . It should be noted that these waveforms of FIG. 4 are based on a simulation and not actual tests. Accordingly, as shown FIG. 4 , the drive circuit (not shown in FIG. 4 ) applies the first signal from zero volts to about 30 volts. As shown, the rate of the voltage increase in this amplitude is very rapid. Between amplitudes of about 30 and just below 80 volts (i.e., a rail voltage), however, the voltage increases much more gradually. These rates may be linear, variable, or both. The exact voltages applied will depend on the design and construction of the switch being controlled.

FIG. 5 is a schematic diagram of one embodiment of a circuit 500 to drive the switch. As will be more fully discussed below, the circuit 500 of FIG. 5 includes a number of transistors and other elements, and two digital sub-circuits 600 and 700 that provide various control signals to the transistors.

FIG. 6( a ) is a schematic of a digital sub-circuit 600 for creating control signals Phi 1 615 , Phi 2 616 and Phi 2 b 617 . FIG. 6( b ) shows the various signals of the circuit in FIG. 6( a ) in response to the input Switch Control signal 614 . Note that for purposes of explaining these circuits, signal “sd” 610 is held low, and therefore signal “sdb” 611 out of inverter 609 is high. As used herein in connection with the signals of digital circuits, the phrase “logic high” and “high” mean a digital logic signal of a first state, and the terms “logic low” and “low” mean a digital logic signal of a second state that is the complement of the first state.

In the circuit 600 of FIG. 6( a ), when the switch is in the open position, the Switch Control signal 614 will be logic low. Through the inverter 601 , this will cause a first input to nor gate 602 to be logic high, and thus the output of nor gate 602 to be low. Accordingly, in steady state the output of inverter 603 will be high and the output of nor gate 604 (Phi 2 616 ) will be low. As a result, the output of nor gate 605 (Phi 2 b 617 ) will be high. Similarly, with Switch Control signal 614 low and Phi 2 616 low, the output of nor gate 606 will be high, and the output of inverter 607 will be low. As a consequence, the output of nand gate 608 (Phi 1 615 ) will be high. Thus at steady state with the input low and signal sd 610 low, Phi 1 615 is high, Phi 2 616 is low, and Phi 2 b 617 is high.

When the user desires to close the switch, the user will cause the Switch Control signal 614 to transition to a logic high. This will cause the output of inverter 601 to go low, but the other input to nor gate 602 temporarily remains high as it was before, so the output of nor gate 602 remains low, and the downstream signals temporarily remain unchanged (including Phi 2 615 at logic low, and Phi 2 b 615 at logic high). In addition, the Switch Control input 614 transition from low to high means the output of nor gate 606 goes low, and thus the output of inverter 607 tries to go high. However, the output transition of inverter 607 is delayed by the need to charge capacitor 612 . When capacitor 612 is charged, the output of inverter 607 will be high, and because sdb 611 is high, both inputs to nand gate 608 are high and thus the output of nand gate 608 (Phi 1 615 ) goes low. After Phi 1 615 goes low, both inputs to nor gate 602 are low, causing the output of nor gate 602 to go high. That signal causes the output of inverter 603 to start to go low, but that transition is delayed by the need to discharge capacitor 613 . When capacitor 613 is discharged, the inputs to nor gate 604 will both be low, causing the output of nor gate 604 (Phi 2 616 ) to go high and thus Phi 2 b 617 to go low. Thus, upon a transition of the input from low to high, and after a short delay due to the charging of capacitor 612 , Phi 1 615 goes low. Then, after a second delay due to the discharging of capacitor 613 , Phi 2 616 goes high, and Phi 2 b 617 goes low. In summary, when the Switch Control input 614 changes from low to high, Phi 1 615 changes from high to low after a short delay, and shortly thereafter Phi 2 616 transitions from low to high and Phi 2 b 617 transitions from high to low.

FIG. 7 is a schematic of a digital sub-circuit 700 for creating pulsed digital signal Edgeout 707 , also in response to the Switch Control input 614 going from low to high. Specifically, the transition of Phi 2 b 617 from high to low in the circuit 600 of FIG. 6( a ) triggers the circuit 700 in FIG. 7 . As described above, when the Switch Control input 614 is low and the circuit is in a steady state, Phi 2 b 617 will be high. As such, the output of nor gate 702 will be low, and the output of inverter 703 will be high, presenting a logic high to one input of nand gate 704 . Similarly, in steady state the output of inverter 701 will present a logic low to a first input of nand gate 705 , while Phi 2 b 617 presents a logic high to the other input of nand gate 705 . Consequently, the output of nand gate 705 will be high. In this state, both inputs to nand gate 704 are high, so that the output of nand gate 704 (signal Edgeout 707 ) is low.

When Phi 2 b 617 transitions to logic low, the output of inverter 701 tries to go high, but that transition is delayed by the need to charge capacitor 706 , so that the output of inverter 701 momentarily stays low. As such, the output of nor gate 702 goes high, and the output of inverter 703 goes low to provide a low input to one input of nand gate 704 . Consequently, the output of nand gate 704 (signal Edgeout 707 ) transitions from low to high. Eventually, capacitor 706 is charged and the output of inverter 701 reaches logic high. Then, the output of nor gate 702 goes back to low, the output of inverter 703 goes back to high, thereby providing a logic high to the one input of nand gate 704 . At the same time, nand gate 705 will have one input high and the other input low, so that the output of nand gate 705 will be high to provide a logic high to the second input of nand gate 704 . As such, the output of nand gate 704 (signal Edgeout 707 ) returns to logic low. In summary, upon the transition of Phi 2 b 617 from logic high to logic low, Edgeout 707 briefly pulses logic high. The duration of the Edgeout 707 pulse will depend on how long it takes the output of inverter 701 to charge capacitor 706 . The duration of the Edgeout 707 pulse will control the duration of the current boost supplied to a current mirror by transistor MN 8 and transistor MN 9 , as described more fully below. The width of the Edgeout pulse is key to turning on the boost current source (through transistor MN 8 and transistor MN 9 ), and hence the time during which the switch arm 105 moves most rapidly towards making contact with stationary conductor 104 .

The operation of the circuit 500 as partially illustrated in FIG. 8 will now be discussed, beginning with the circuit in steady state, with the Switch Control input signal 614 low, leaving the switch open. As discussed above, in this state Phi 1 615 is high, Phi 2 616 is low, Phi 2 b 617 is high, and Edgeout 707 is low. A bias current of preferably 2 micro-Amperes flows through transistor MN 4 , which forms a current mirror with transistor MN 8 and a second current mirror with transistor MN 3 . In this state, a portion of the bias current in transistor MN 4 is mirrored in transistor MN 3 , producing a current of preferably 500 nano-Amperes. Because Edgeout 707 is low, no appreciable current flows in transistor MN 9 or transistor MN 8 . Because Phi 2 616 is low and Phi 2 b 617 is high, transistor MN 2 is off (non-conducting) and transistor MN 1 is on (conducting) so that all current flowing through transistor MN 3 must also flow through transistor MN 1 . This current flow tends to pull the gates of transistor MP 2 towards ground, causing transistor MP 2 to electrically pull the gates of transistor MP 1 , transistor MP 5 and transistor MP 4 towards voltage rail (Vcc). As a result, transistors MP 5 and MP 4 are effectively non-conducting, so that transistor MP 4 does not inject or sink current from the output node 501 . At the same time, Phi 2 616 high causes transistor MN 5 to turn on (conducting), which drains charge on the switch gate 102 to ground via the output node 501 , thereby depriving the switch arm 105 from any force to pull it downwards, and consequently the switch 100 is open.

When the user wants to close the switch, the user causes the input Switch Control signal 614 to go high. As discussed above, this causes certain changes in control signals Phi 1 615 , Phi 2 616 , and Phi 2 b 617 , and causes Edgeout 707 to pulse. The operation of the circuit 500 as partially illustrated in FIG. 9 will now be discussed. After the Switch Control signal 614 goes high, Phi 1 615 will go low, thereby turning off transistor MN 5 , so that the gate electrode 102 of the switch is no longer shunted to ground. Initially, transistor MP 4 remains off (non-conducting) so that there is no path for current to flow directly between Vcc and ground. The signals Phi 1 615 , Phi 2 616 and Phi 2 b 617 are phased in time to assure that transistor MN 5 and transistor MP 4 are not conducting simultaneously. After a brief delay, Phi 2 616 will go high and Phi 2 b 617 will go low, causing transistor MN 2 to turn on (conducting) and transistor MN 1 to turn off (non-conducting). Consequently, transistors MP 5 and transistor MP 4 also are released to conduct current. The current through transistor MN 3 (preferably 500 nano-Amperes) is now forced to flow through transistor MN 2 , and therefore through transistor MP 5 . Transistor MP 4 forms a current mirror with transistor MP 5 , with a gain of 4. It is known in the art to select a current mirroring transistor to provide a current gain, for example by making the mirroring transistor (in this case, transistor MP 4 ) larger than the conducting transistor (in this case, transistor MP 5 ). As a result, transistor MP 4 conducts the amplified mirrored current (preferably 2 micro-Amperes) to the output node 501 . The output node 501 is attached to the gate 102 of the switch, which is capacitive and acts to integrate the current flowing to it from the drive circuit, thereby causing the voltage on the gate 102 to ramp upwards (i.e., i=C dV/dt).

As also discussed above, the transition of the Switch Control 614 signal to logic high will cause Edgeout 707 to pulse to logic high. This will cause transistor MN 9 to turn on (conducting), which will allow transistor MN 8 to mirror a portion of the current in transistor MN 4 ; preferably 2.5 micro-Amperes. The current in transistor MN 8 will supplement the current in transistor MN 3 that flows through transistor MN 2 , and the combined currents (preferably 3 micro-Amperes) will ultimately be amplified and mirrored by transistor MP 4 to provide a current burst of 12 micro-Amperes to the output node 501 . In turn, this causes the voltage on the switch gate 102 to ramp quickly toward the threshold voltage. Preferably the duration of Edgeout 707 is set to maintain this current flow until the voltage on the switch gate approaches the threshold voltage.

As further discussed above, the Edgeout 707 pulse will end, thereby turning off transistor MN 9 (non-conducting). The operation of the circuit 500 as partially illustrated in FIG. 10 will now be discussed. In this state, the current in transistor MN 3 is the only current being amplified and mirrored and provided to the output node 501 . As such, the voltage on the switch gate will continue to ramp upwards, but now at a slower rate of change. At some point the voltage on the switch gate electrode exceeds the threshold voltage (Vth), at which time the switch arm makes contact with the drain electrode.

In accordance with the foregoing, the voltage on the switch gate electrode increases rapidly at the beginning, but then the voltage ramp slows. The voltage quickly reaches a point where it is strong enough to move the MEMS switch cantilever downward, which is important so that there is minimal lag time between the changing of the Switch Control 614 signal that commands the circuit to close the switch, and the actual closing of the switch. Later, the voltage on the switch gate increases more slowly, up to an ultimate voltage that is strong enough to hold the switch arm securely in the downward, closed position. Preferably the operation of the drive circuit will cause the arm to contact the drain electrode without bouncing or damaging the arm.

When the user desires to open the switch, the user will cause the Switch Control signal 614 to go low. The digital circuit discussed above will cause the driver circuit 500 to revert to the state discussed above in connection with FIGS. 6 and 8 . As before, owing to the delays inherent in the timing generation circuit, the digital control signals Phi 1 615 , Phi 2 615 and Phi 2 b 615 are phased in time to assure that transistor MN 5 and transistor MP 4 are not conducting simultaneously. As such, transistor MN 5 will again drain the current from the switch gate electrode, thereby removing the force holding the arm in the downward, closed position, and allowing the switch to move back to the up, open circuit position.

FIG. 11 is a schematic diagram of an alternate embodiment of a switch drive circuit. The switch drive circuit 1100 of FIG. 11 drives the switch with a voltage signal 1104 . Voltage signal V 1 1101 and voltage signal V 2 1101 are both input to summing junction 1103 . As is known in the art, the summing junction 1103 will sum voltage signal V 1 and voltage signal V 2 to produce voltage signal 1104 . The level of voltage signal V 1 and the level of voltage signal V 2 combine to produce voltage signal 1104 having at least a first level and a second level. Voltage signal 1104 is then applied to the gate of the switch (not shown in FIG. 11 ) to control the operation of the switch. The level of voltage signal V 1 and the level of voltage signal V 2 are the rate of change of the respective voltages. The level of voltage signal V 1 and the level of voltage signal V 2 may change with time in order to produce the desired level of the voltage signal 1104 .

Although the above discussion discloses various exemplary embodiments of the invention, it should be apparent that those skilled in the art can make various modifications that will achieve some of the advantages of the invention without departing from the true scope of the invention. The described embodiments are to be considered in all respects only as illustrative and not restrictive.