Thin film transistor array panel for liquid crystal display and method for manufacturing the same

A method of fabricating a thin film transistor array panel, the method comprising:nforming a gate line assembly and a storage capacitor line assembly on an insulating substrate such that the gate line assembly has a gate line and a gate electrode;forming a gate insulating layer such that the gate insulating layer covers the gate line assembly and the storage capacitor line assembly;forming a semiconductor pattern on the gate insulating layer;forming a data line assembly and a storage capacitor conductive pattern on the gate insulating layer overlaid with the semiconductor pattern such that the data line assembly has a data line, a source electrode and a drain electrode, and the storage capacitor conductive pattern are partially overlapped with the storage capacitor line assembly to thereby form a first storage capacitor;forming a passivation layer such that the passivation layer covers the data line assembly, the storage capacitor conductive pattern and the semiconductor pattern;forming first and second contact holes at the passivation layer such that the first and the second contact holes expose the drain electrodes and the storage capacitor conductive pattern, respectively; andforming a pixel electrode on the passivation layer such that the pixel electrode is connected to the drain electrode and the storage capacitor conductive patterns through the first and the second contact holes while forming a second storage capacitor in association with parts of the storage capacitor lines assembly,wherein the storage capacitor conductive pattern has an island shape.

A method of fabricating a thin film transistor array panel, the method comprising:nforming a gate line assembly on an insulating substrate such that the gate line assembly has a first gate line, a gate electrode connected to the first gate line, and a second gate line spaced apart from the first gate line with a predetermined distance while proceeding parallel to the first gate line;forming a gate insulating layer such that the gate insulating layer covers the gate line assembly;forming a semiconductor pattern on the gate insulating layer such that the semiconductor pattern is overlapped with the gate electrode;forming a data line assembly and a storage capacitor conductive pattern on the gate insulating layer overlaid with the semiconductor pattern such that the data line assembly has a data line crossing over the first and the second gate lines, a source electrode and a drain electrode, and the storage capacitor conductive pattern is partially overlapped with the second gate line to thereby form a first storage capacitor;forming a passivation layer such that the passivation layer covers the data line assembly, the storage capacitor conductive pattern and the semiconductor pattern;forming first and second contact holes at the passivation layer such that the first and the second contact holes expose the drain electrode and the storage capacitor conductive pattern, respectively; andforming a pixel electrodes electrode on the passivation layer such that the pixel electrode is connected to the drain electrode and the storage capacitor conductive pattern through the first and the second contact holes while forming a second storage capacitor in association with parts of the second gate line,wherein the storage capacitor conductive pattern has an island shape.

A method of fabricating a thin film transistor array panel, the method comprising:nforming a gate line assembly and a storage capacitor electrode line on an insulating substrate such that the gate line assembly has a gate line and a gate electrode;forming a gate insulating layer such that the gate insulating layer covers the gate line assembly and the storage capacitor electrode line;forming a first contact hole at the gate insulating layer such that the first contact hole expose the storage capacitor electrode line;forming a semiconductor pattern on the gate insulating layer such that the semiconductor pattern is overlapped with the gate electrode;forming a data line assembly and a storage capacitor conductive pattern on the gate insulating layer overlaid with the semiconductor pattern such that the data line assembly has a data line, a source electrode and a drain electrode, and the storage capacitor conductive pattern is connected to the storage capacitor electrode line through the first contact hole;forming a passivation layer such that the passivation layer covers the data line assembly, the storage capacitor conductive pattern and the semiconductor pattern;forming a second contact hole at the passivation layer such that the second contact hole exposes the drain electrode; andforming a pixel electrode on the passivation layer such that the pixel electrode is connected to the drain electrode through the second contact hole, the pixel electrode being overlapped with the storage capacitor conductive pattern to thereby form a first storage capacitor while being partially overlapped with the storage capacitor electrode line to thereby form second storage capacitor.

A method of fabricating a thin film transistor array panel, the method comprising:nforming a gate line assembly on an insulating substrate such that the gate line assembly has a first gate line, a gate electrode connected to the first gate line, and a second gate line spaced apart from the first gate line with a predetermined distance while proceeding parallel to the first gate line;forming a gate insulating layer such that the gate insulating layer covers the gate line assembly;forming a first contact hole at the gate insulating layer such that the first contact hole partially expose the second gate line;forming a semiconductor pattern on the gate insulating layer such that the semiconductor pattern is overlapped with the gate electrode;forming a data line assembly and a storage capacitor conductive pattern on the gate insulating layer overlaid with the semiconductor pattern such that the data line assembly has a data line crossing over the first and the second gate lines, a source electrode and a drain electrode, and the storage capacitor conductive pattern is connected to the second gate line through the first contact hole;forming a passivation layer such that the passivation layer covers the data line assembly, the storage capacitor conductive pattern and the semiconductor pattern;forming a second contact hole at the passivation layer such that the second contact hole exposes the drain electrode; andforming a pixel electrode on the passivation layer such that the pixel electrode is connected to the drain electrode through the second contact hole, the pixel electrode being overlapped with the storage capacitor conductive pattern to thereby form a first storage capacitor while being partially overlapped with the second gate line to thereby form a second storage capacitor.