A thin film transistor array panel according to an embodiment includes: a substrate; a plurality of gate line formed on the substrate; a plurality of first capacitor electrodes formed on the substrate and separated from the gate lines; a plurality of data line intersecting the gate lines; a plurality of thin film transistor connected to the gate lines and the data lines; a plurality of second capacitor electrodes disposed on the first electrode; a plurality of interconnections connected to the second capacitor electrodes and the thin film transistor and disposed symmetrical to the data lines; and a plurality of pixel electrode, each pixel electrode including a first subpixel electrode connected to one of the thin film transistors and a second subpixel electrode connected to one of the first capacitor electrodes.

Claims

19 · 1 independent · depth 7

19 granted claims

›1.independentA liquid crystal display, comprising:na first substrate;a gate line formed on the first substrate;a first capacitor electrode formed on the first subs…+18

›2.↳ 1The liquid crystal display of claim 1, wherein the first electrode is substantially parallel with the date line and the distance between the first ele…d2+8

›3.↳ 2The liquid crystal display of claim 2, further comprising:nat least one structural member connected to the thin film transistor; andat least one stora…d3+5

›9.↳ 2The liquid crystal display of claim 2, wherein the pixel electrode overlaps the first electrodes.d3

›10.↳ 2The liquid crystal display of claim 2, wherein the first electrodes overlap the first capacitor electrode.d3

›11.↳ 1The liquid crystal display of claim 1, wherein the second capacitor electrode has a through-hole, and the second subpixel electrode and the first capa…d2

›12.↳ 1The liquid crystal display of claim 1, wherein one of the first capacitor electrode and the second capacitor electrode is disposed substantially symme…d2

›13.↳ 1The liquid crystal display of claim 1, wherein the shielding electrode overlaps a predetermined portion of one of the data line and the gate line.d2+2

›16.↳ 1The liquid crystal display of claim 1, wherein at least one of the first subpixel electrode and the second subpixel electrode has a partitioning membe…d2+1

›18.↳ 1The liquid crystal display of claim 1, wherein the pixel electrode overlaps the first electrodes.d2

›19.↳ 1The liquid crystal display of claim 1, wherein the first electrodes overlap the first capacitor electrode.d2

Classifications

6 codes

IPC · International Patent Classification

Section G — Physics

G02F1/1343

USPC · US Patent Classification

349/38349/129349/139349/111349/144

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Pendency

1.5 y

544 days filing → grant

Office actions

non-final + final

Responses

1 RCE

Examiner

Thoi V Duong

art unit 2871 · TC 2800

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Citations: 2 back · 0 forward

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Priority chain

1 priority documents

›Priority documents — 1

Type	Document	Date
related publication	US 20100025689 A1	4 Feb 2010

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