An integrated circuit synchronous read channel for receiving digitized read signals representing digitized samples of a read signal of a magnetic storage device and recovering digital data represented thereby, the integrated circuit comprising:nat least one detector, responsive to the digitized read signals, that operates to:ndetect characteristics of the digitized read signals indicative of storage media transitions; andreceive a stream of the digitized read signals and determine a corresponding sequence of binary digital signals likely to be represented by the received stream of the digitized read signals;a timing recovery circuit, responsive to the digitized read signals and an output of the at least one detector, that operates to provide a timing control signal for controlling the timing of digitized samples of the read signal; andan RLL (d,k) decoder that operates to provide a run length limited decoded output by decoding the sequence of binary digital signals determined by the at least one detector.
›2.↳ 1The integrated circuit synchronous read channel of claim 1 further comprising a digital pulse shaping filter that operates to modify the digitized rea…d2+3
The integrated circuit synchronous read channel of claim 1 further comprising a digital pulse shaping filter that operates to modify the digitized read signals prior to receipt thereof by at least one of (i) the at least one detector and (ii) the timing recovery circuit.
›3.↳ 2The integrated circuit synchronous read channel of claim 2 wherein the digital pulse shaping filter comprises variable filter parameters.d3
The integrated circuit synchronous read channel of claim 2 wherein the digital pulse shaping filter comprises variable filter parameters.
›4.↳ 2The integrated circuit synchronous read channel of claim 2 wherein the digital pulse shaping filter comprises programmable filter parameters.d3
The integrated circuit synchronous read channel of claim 2 wherein the digital pulse shaping filter comprises programmable filter parameters.
›5.↳ 2The integrated circuit synchronous read channel of claim 2 further comprising a spectrum smoothing filter that operates to filter the digitized read s…d3
The integrated circuit synchronous read channel of claim 2 further comprising a spectrum smoothing filter that operates to filter the digitized read signals prior to processing by the at least one detector.
›6.↳ 1The integrated circuit synchronous read channel of claim 1, wherein the at least one detector allows selection between center and side sampling of the…d2
The integrated circuit synchronous read channel of claim 1, wherein the at least one detector allows selection between center and side sampling of the digitized read signals.
›7.↳ 1The integrated circuit synchronous read channel of claim 1, wherein the at least one detector accommodates pulse asymmetry in the digitized read signa…d2
The integrated circuit synchronous read channel of claim 1, wherein the at least one detector accommodates pulse asymmetry in the digitized read signals.
›8.↳ 1The integrated circuit synchronous read channel of claim 1, wherein the at least one detector comprises a partial response sequence detector.d2
The integrated circuit synchronous read channel of claim 1, wherein the at least one detector comprises a partial response sequence detector.
›9.↳ 1The integrated circuit synchronous read channel of claim 1, wherein the timing recovery circuit operates in a plurality of different modes comprising …d2+1
The integrated circuit synchronous read channel of claim 1, wherein the timing recovery circuit operates in a plurality of different modes comprising an acquisition mode and a tracking mode.
›17.↳ 9The integrated circuit synchronous read channel of claim 9, wherein the acquisition mode corresponds to a first frequency control range and a first fr…d3
The integrated circuit synchronous read channel of claim 9, wherein the acquisition mode corresponds to a first frequency control range and a first frequency control resolution, and the tracking mode corresponds to a second frequency control range different from the first frequency control range and a second frequency control resolution different from the first frequency control resolution.
›10.↳ 1The integrated circuit synchronous read channel of claim 1, wherein the timing recovery circuit is programmable.d2
The integrated circuit synchronous read channel of claim 1, wherein the timing recovery circuit is programmable.
›11.↳ 1The integrated circuit synchronous read channel of claim 1, wherein the timing recovery circuit operates to compute at least one of phase error and fr…d2
The integrated circuit synchronous read channel of claim 1, wherein the timing recovery circuit operates to compute at least one of phase error and frequency error.
›12.↳ 1The integrated circuit synchronous read channel of claim 1, wherein the timing recovery circuit operates to compute timing error at transition times.d2
The integrated circuit synchronous read channel of claim 1, wherein the timing recovery circuit operates to compute timing error at transition times.
›13.↳ 1The integrated circuit synchronous read channel of claim 1, wherein the RLL (d, k) decoder operates to provide a run length limited decoded output by …d2
The integrated circuit synchronous read channel of claim 1, wherein the RLL (d, k) decoder operates to provide a run length limited decoded output by decoding a sequence of binary digital signals from the at least one detector.
›14.↳ 1The integrated circuit synchronous read channel of claim 1, wherein the digitized read signals comprise a plurality of parallel digital signals.d2
The integrated circuit synchronous read channel of claim 1, wherein the digitized read signals comprise a plurality of parallel digital signals.
›15.↳ 1The integrated circuit synchronous read channel of claim 1, wherein the type of data output from the RLL (d, k) decoder is user-selectable.d2
The integrated circuit synchronous read channel of claim 1, wherein the type of data output from the RLL (d, k) decoder is user-selectable.
›16.↳ 1The integrated circuit synchronous read channel of claim 1, wherein the timing recovery circuit operates to feed back the timing control signal to cir…d2
The integrated circuit synchronous read channel of claim 1, wherein the timing recovery circuit operates to feed back the timing control signal to circuitry that samples the read signal of the magnetic storage device.
›18.↳ 1The integrated circuit synchronous read channel of claim 1, wherein the at least one detector comprises a Viterbi detector.d2
The integrated circuit synchronous read channel of claim 1, wherein the at least one detector comprises a Viterbi detector.
›19.↳ 1The integrated circuit synchronous read channel of claim 1, wherein d=1.d2
The integrated circuit synchronous read channel of claim 1, wherein d=1.
›20.↳ 1The integrated circuit synchronous read channel of claim 1, wherein the at least one detector comprises a digital peak detector and a sequence detecto…d2
The integrated circuit synchronous read channel of claim 1, wherein the at least one detector comprises a digital peak detector and a sequence detector.
