Manufacturing method of flash memory device comprising gate columns penetrating through a cell stack

A method for manufacturing a flash memory device comprising:nforming a semiconductor layer for providing channel and junction areas over a substrate;forming an interlayer isolation layer for insulation over the semiconductor layer;forming a cell stack by repeatedly stacking the semiconductor layer and the interlayer isolation layer;forming an array of through holes that penetrate through the cell stack;forming a trap layered stack for storing charges over the inner wall of the through holes; andforming a gate column for filling in the through hole over the trap layered stack,wherein the junction areas are formed in the semiconductor layer in a shape of a stripe.

A method for manufacturing a flash memory device comprising:nforming a semiconductor layer over a substrate;forming junction areas for setting areas therebetween to channel areas in the semiconductor layer in a shape of a stripe;forming an interlayer isolation layer for insulation over the semiconductor layer;forming a cell stack by repeatedly stacking the semiconductor layer formed with the junction areas and the interlayer isolation layer;forming an array of through holes that penetrate through the cell stack and cut through the junction areas to dispose the junction areas at both sides thereof;forming a trap layered stack for storing charges over the inner wall of the through holes; andforming a gate column for filling in the through hole over the trap layered stack.

A method for manufacturing a flash memory device comprising:nforming a semiconductor layer over a substrate;forming junction areas for setting areas therebetween to channel areas in the semiconductor layer in a shape of a stripe;forming an interlayer isolation layer for insulation over the semiconductor layer;forming a cell stack by repeatedly stacking the semiconductor layer formed with the junction areas and the interlayer isolation layer;forming an array of through holes that penetrate through the cell stack and cut through the junction areas to dispose the junction areas at both sides thereof;forming a trap layered stack for storing charges over an inner wall of the through holes;forming a gate column for filling in the through hole overs the trap layered stack;forming an etch mask that covers the gate columns and the junction areas and exposes some portion of the channel area between the rows of the gate columns in a direction parallel to the direction in which the junction areas and the gate columns are arranged;forming an interstack isolation trench by selectively removing the portion of the cell stack exposed by the etch mask; andforming an interstack isolation layer for isolating between the cell strings by filling in the interstack isolation trench.

A method for manufacturing a flash memory device comprising:nforming a semiconductor layer over a substrate;forming junction areas for setting areas therebetween to channel areas in the semiconductor layer in a shape of a stripe;forming a first sub interlayer isolation layer for insulation over the semiconductor layer;forming a contact connected to the junction area, the contact penetrating through the first sub interlayer isolation layer;forming a bit line connected to the contact over the first sub interlayer isolation layer;forming an interlayer insulation layer provided with the bit line buried therein by forming a second sub interlayer isolation layer for covering and insulating the bit line;forming a cell stack by repeatedly stacking the semiconductor layer formed with the junction areas and the interlayer isolation layer;forming an array of through holes that penetrate through the cell stack and cut through the junction areas to dispose the junction areas at both sides thereof;forming a trap layered stack for storing charges over an inner wall of the through holes; andforming a gate column for filling in the through holes over the trap layered stack.

A method for manufacturing a flash memory device comprising:nforming a semiconductor layer over a substrate;forming junction areas for setting areas therebetween to channel areas in the semiconductor layer in a shape of a stripe;forming a first sub interlayer isolation layer for insulation over the semiconductor layer;forming a contact connected to the junction areas, the contact penetrating through the first sub interlayer isolation layer;forming a bit line over the first sub interlayer isolation layer, the bit line being connected to the contact and extending in a direction perpendicular to the cell string direction;forming an interlayer insulation layer provided with the bit line buried therein by forming a second sub interlayer isolation layer for covering and insulating the bit line;forming a cell stack by repeatedly stacking the semiconductor layer formed with the junction areas and the interlayer isolation layer;forming an array of through holes that penetrate through the cell stack and cut through the junction areas to dispose the junction areas at both sides thereof;forming a trap layered stack for storing charges over an inner wall of the through hole; andforming a gate column for filling in the through hole over the trap layered stack.