A digital low dropout (LDO) regulator for generating an output voltage on an output from a source of an input voltage, the LDO comprising:nmeans for voltage generating to generate the output voltage,wherein:nthe means for voltage generating including at least two parallel connected means for switching responsive to corresponding switch control signals to regulate a flow of energy from the input voltage source to the output; andeach of the at least two parallel connected means for switching having an on-state and an off-state; andmeans for digital controlling to sense the output voltage and to generate the switch control signals in response to the output such that the output voltage is regulated to a predetermined amplitude,wherein:nthe means for voltage generating includes a coupled inductor regulator;the at least two parallel connected means for switching are a conduction switch array that is responsive to the switch control signals to generate the output voltage;each of the switch control signals have a duty cycle of approximately 50%; andthe coupled inductor regulator comprises:nat least two means for conduction switching to conduct energy from the source of the input voltage to the output;at least two inductors in communication with the at least two means for conduction switching,wherein:nthe at least two inductors are wound together on a common core;each of the at least two inductors has a polarity such that DC currents in the inductors cancel each other; andthe at least two inductors have coefficient of coupling approximately equal to one; andat least two means for freewheeling switching in communication with the at least two means for conduction switching to provide a path for current during non-conduction periods;the switch control signals each have a duty cycle of approximately 50% and are used to control the at least two means for conduction switching;each of the at least two means for conduction switching comprises a conduction switch array;the at least two means for conduction switching, the at least two inductors, and the at least two means for freewheeling switching are connected in a boost configuration such that the output voltage is approximately twice the amplitude of the input voltage; andthe boost configuration includes two boost regulators each operating at approximately 50% duty cycle, each boost regulator including; anda means for conduction switching in communication with a means for freewheeling switching and an inductor,wherein:nthe means for conduction switching to provide current during a conduction period from the a high side of the source of the input voltage through the inductor to a low side of the source of the input voltage; andthe means for freewheeling switching to provide a conduction path during the non-conduction period for current flowing from the high side of the source of the input voltage through the inductor to the output.
›23.↳ 22The digital LDO regulator of claim 22, wherein:nthe means for voltage generating is a digital resistor; andthe at least two parallel connected means f…d2
The digital LDO regulator of claim 22, wherein:nthe means for voltage generating is a digital resistor; andthe at least two parallel connected means for switching are a switch array.
›24.↳ 22The digital LDO regulator of claim 22, wherein the means for digital controlling includes:nmeans for analog-to-digital converting to generate a digita…d2+2
The digital LDO regulator of claim 22, wherein the means for digital controlling includes:nmeans for analog-to-digital converting to generate a digital signal of the output voltage; andmeans for generating switch control signals, responsive to the digital signal, to generate the switch control signals.
›25.↳ 24The digital LDO regulator of claim 24, wherein the means for generating switch control signals is a digital signal processor (DSP).d3+1
The digital LDO regulator of claim 24, wherein the means for generating switch control signals is a digital signal processor (DSP).
›26.↳ 25The digital LDO regulator of claim 25, wherein:nthe means for generating switch control signals includes a burst mode to operate the switch module at …d4
The digital LDO regulator of claim 25, wherein:nthe means for generating switch control signals includes a burst mode to operate the switch module at low output current; andthe burst mode includes duty cycle control of the at least two parallel connected means for switching to regulate the output voltage.
›27.↳ 22The digital LDO regulator of claim 22, wherein the at least two parallel connected means for switching includes:na group of parallel switches responsi…d2
The digital LDO regulator of claim 22, wherein the at least two parallel connected means for switching includes:na group of parallel switches responsive to a first one of the switch control signals; anda single switch responsive to a second one of the switch control signals.
›28.↳ 22The digital LDO regulator of claim 22, wherein the coefficient of coupling is approximately at least 0.99.d2
The digital LDO regulator of claim 22, wherein the coefficient of coupling is approximately at least 0.99.
›29.↳ 22The digital LDO regulator of claim 22, wherein the at least two means for conduction switching, the at least two inductors, and the at least two means…d2+1
The digital LDO regulator of claim 22, wherein the at least two means for conduction switching, the at least two inductors, and the at least two means for freewheeling switching are connected in a buck configuration such that the output voltage is approximately one-half the amplitude of the input voltage.
›30.↳ 29The digital LDO regulator of claim 29, wherein:nthe buck configuration includes two buck regulators each operating at approximately 50% duty cycle;eac…d3
The digital LDO regulator of claim 29, wherein:nthe buck configuration includes two buck regulators each operating at approximately 50% duty cycle;each buck regulator includes a means for conduction switching in communication with a means for freewheeling switching and an inductor;the means for conduction switching configured to provide current during a conduction period from the source of the input voltage through the inductor to the output; andthe means for freewheeling switching to provide a conduction path during the non-conduction period for current flowing through the inductor to the output.
›31.↳ 22The digital LDO regulator of claim 22, wherein the at least two means for conduction switching, the at least two inductors, and the at least two means…d2+1
The digital LDO regulator of claim 22, wherein the at least two means for conduction switching, the at least two inductors, and the at least two means for freewheeling switching are connected in a 1:−1 configuration such that the output voltage is approximately a negative of the input voltage.
›32.↳ 31The digital LDO regulator of claim 31, wherein:nthe 1:−1 configuration includes two flyback regulators each operating at approximately 50% duty cycl…d3
The digital LDO regulator of claim 31, wherein:nthe 1:−1 configuration includes two flyback regulators each operating at approximately 50% duty cycle;each flyback regulator includes a means for conduction switching in communication with a means for freewheeling switching and an inductor;the means for conduction switching configured to provide current during a conduction period from the a high side of the source of the input voltage through the inductor to a low side of the source of the input voltage; andthe means for freewheeling switching to provide a conduction path during the non-conduction period for current flowing from the output through the inductor to the low side of the source of the input voltage.
›33.↳ 22A multi-chip module comprising:na first semiconductor die comprising the digital LDO regulator of claim 22; anda second semiconductor die comprising m…d2+2
A multi-chip module comprising:na first semiconductor die comprising the digital LDO regulator of claim 22; anda second semiconductor die comprising means for performing digital logic operations.
›34.↳ 33The multi-chip module of claim 33, wherein the means for performing digital logic operations includes complex logic operations.d3
The multi-chip module of claim 33, wherein the means for performing digital logic operations includes complex logic operations.
›35.↳ 33The multi-chip module of claim 33, wherein the means for performing digital logic operations includes a processor.d3
The multi-chip module of claim 33, wherein the means for performing digital logic operations includes a processor.
›36.↳ 22A semiconductor device formed on a single semiconductor die, the semiconductor device comprising:nthe digital LDO regulator of claim 22; andmeans for …d2+2
A semiconductor device formed on a single semiconductor die, the semiconductor device comprising:nthe digital LDO regulator of claim 22; andmeans for performing digital logic operations.
›37.↳ 36The semiconductor device of claim 36, wherein the means for performing digital logic operations performs complex logic operations.d3
The semiconductor device of claim 36, wherein the means for performing digital logic operations performs complex logic operations.
›38.↳ 36The semiconductor device of claim 36, wherein the means for performing digital logic operations includes a processor.d3
The semiconductor device of claim 36, wherein the means for performing digital logic operations includes a processor.
›42.↳ 22The digital LDO regulator of claim 22, wherein:nthe means for voltage generating is a coupled inductor regulator comprising at least a first switch pa…d2
The digital LDO regulator of claim 22, wherein:nthe means for voltage generating is a coupled inductor regulator comprising at least a first switch pair and a second switch pair connected together through corresponding coupled inductors;each of the first switch pair and the second switch pair includes a conduction switch array in communication with a freewheeling switch array;the conduction switch array of the at least first switch pair includes X≧1 parallel connected means for switching;the conduction switch array of the at least second switch pair includes N≧1 parallel connected means for switching;the freewheeling switch array of the at least first switch pair includes Y≧1 parallel connected means for switching; andthe freewheeling switch array of the at least second switch pair includes M≧1 parallel connected means for switching.
›46.↳ 22The digital LDO regulator of claim 22, wherein:na first conduction time of one of the at least two means for conduction switching is separated from a …d2
The digital LDO regulator of claim 22, wherein:na first conduction time of one of the at least two means for conduction switching is separated from a second conduction time of another of the at least two means for conduction switching by non-conduction time; anda duration of the non-conduction time is substantially less than a duration of both the first conduction time and the second conduction time.
›47.↳ 22The digital LDO regulator of claim 22, wherein the at least two means for conduction switching have a combined conduction time that approaches but is …d2
The digital LDO regulator of claim 22, wherein the at least two means for conduction switching have a combined conduction time that approaches but is less than 100%.
›48.↳ 22The digital LDO regulator of claim 22, wherein:none of the at least two means for conduction switching receives a first drive signal;another of the at…d2
The digital LDO regulator of claim 22, wherein:none of the at least two means for conduction switching receives a first drive signal;another of the at least two means for conduction switching receives a second drive signal;one of the at least two means for freewheeling switching receives the second drive signal;another of the at least two means for freewheeling switching receives the first drive signal; andthe first and second drive signals are the same signal with a phase offset that is equal to 360 degrees divided by a total number of the conduction switches.