Frequency jittering control for varying the switching frequency of a power supply

The present invention generally relates to a switching mode power supply and, more particularly, to a frequency jittering circuit and method for varying the switching frequency of a power supply.

Most switching mode power supplies operate at a fixed and fast switching frequency. Unfortunately, a strong noise would be generated at such switching frequency and its relative harmonic, thereby inducing loud electromagnetic interference (EMI). Jittering or dithering switching frequency can distribute the noise's energy to a broad band, and thus depresses the noise and improves the performance in conduction of EMI. As is well known in the art, the switching frequency of a switching mode power supply depends on the clock frequency of the oscillator in the power supply. For further detail, FIG. 1 shows a conventional oscillator 100 , in which a comparator 102 will trigger a comparison signal COMP 1 to a set input S of a flip-flop 110 when the voltage Vosc on the capacitor C-osc is lower than a lower limit VREF 1 of a hysteretic band, causing the output Q of the flip-flop 110 to be high, and thereby turning off a switch S 4 for a current source 108 to stop discharging the capacitor C_osc, and turning on a switch S 3 for a current source 106 to charge the capacitor C_osc. When the voltage Vosc increases to touch an upper limit VREF 2 of the hysteretic band, a comparator 104 triggers a comparison signal COMP 2 to a reset input R of the flip-flop 110 , causing the output Q of the flip-flop 110 to be low, and thereby turning off the switch S 3 for current source 106 to stop charging the capacitor C_osc, and turning on the switch S 4 for the current source 108 to discharge the capacitor C_osc. A one shot circuit 112 generates a clock CLK according to the output Q of the flip-flop 110 . As shown in the oscillator 100 of FIG. 1 , the frequency of the clock CLK is determined by the charging current IREF 1 , the discharging current IREF 2 , the capacitance C_osc and the hysteretic band corresponding to the lower limit VREF 1 and the upper limit VREF 2 . U.S. Pat. No. 6,249,876 to Balakrishnan et al. disclosed a frequency jittering control for varying the switching frequency of a power supply by adjusting the charging and discharging currents in the oscillator circuit of the power supply, and thus reduces the EMI emission. However, this art requires a huge capacitor to be charged and discharged, which is disadvantageous to cost reduction and chip circuit integration.

Therefore, it is desired a smaller and cost-effective frequency jittering circuit for varying the switching frequency of a power supply.

An object of the present invention is to provide a frequency jittering circuit and method for varying the switching frequency of a power supply.

In a frequency jittering circuit according to the present invention, the hysteretic band of an oscillator is varied to provide a clock having a jitter frequency, so as to obtain a jittering switching frequency when a switching mode power supply operates on the clock.

In one embodiment, a triangle wave is provided such that the upper limit of the hysteretic band varies with time, and when the upper limit of the hysteretic band increases or decreases, the clock frequency decreases or increases accordingly.

These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a conventional oscillator circuit;

FIG. 2 is an embodiment according to the present invention;

FIG. 3 is an embodiment for the oscillator shown in FIG. 2 ;

FIG. 4 is a waveform diagram showing various signals in the circuits of FIGS. 2 and 3 ; and

FIG. 5 is another embodiment for the oscillator shown in FIG. 2 .

As an embodiment according to the present invention shown in FIG. 2 , a frequency jittering circuit 200 has a hysteretic band modulator 202 to modulate the hysteretic band for generating a clock for a switching mode power supply. The hysteretic band modulator 202 generates a low-frequency signal VC 5 under clocking of a clock CLK, and a gain circuit 210 includes an amplifier 212 of gain E 1 to amplify the low-frequency signal VC 5 to thereby generate a modifying signal V_tri for an oscillator 214 . The modifying signal V_tri modifies the hysteretic band of the oscillator 214 , and thus the hysteretic band varies with time. In the hysteretic band modulator 202 , a current source 204 is connected to a capacitor C 5 via a switch S 1 , a current source 206 is connected to the capacitor C 5 via a switch S 2 , and a voltage comparator 208 detects the low-frequency signal VC 5 to generate a comparison signal COMP 3 . The comparison signal COMP 3 and the clock CLK are used to switch the switches S 1 and S 2 such that the current sources 204 and 206 charge and discharge the capacitor C 5 , respectively, so as to produce the low-frequency signal VC 5 . FIG. 3 is an embodiment for the oscillator 214 shown in FIG. 2 , in which an adder 300 combines a signal VREF 2 and the modifying signal V_tri to generate an upper limit VREF 3 for the hysteretic band. When the voltage Vosc on the capacitor C_osc is lower than the lower limit VREF 1 of the hysteretic band, a comparator 302 triggers a comparison signal COMP 4 to a set input S of a flip-flop 310 , and when the voltage Vosc is higher than the upper limit VREF 3 of the hysteretic band, a comparator 304 triggers a comparison signal COMP 5 to a reset input R of the flip-flop 310 . Therefore, in accordance with the comparison signals CMOP 4 and COMP 5 , the flip-flop 310 switches the switches S 3 and S 4 by its output Q such that the capacitor C_osc is charged and discharged by current sources 306 and 308 , respectively. A one shot circuit 312 generates the clock CLK in accordance with the output Q of the flip-flop 310 . The clock CLK is provided for a switching mode power supply, and thus the jittering frequency of the clock CLK varies the switching frequency of the power supply.

FIG. 4 is a waveform diagram showing various signals in the circuits of FIGS. 2 and 3 , in which waveform 400 represents the upper limit VREF 3 of the hysteretic band, waveform 402 represents the voltage Vosc, and waveform 404 represents the low-frequency signal VC 5 . At time t 1 , the low-frequency signal VC 5 equals to V 1 , and thus the output COMP 3 of the comparator 208 is high, which enables a logic unit U 1 and disables a logic unit U 2 ; meanwhile, the non-inverting input of the comparator 208 is switched to a voltage V 2 . During the logic unit U 2 is disabled, the switch S 2 remains off, and the switch S 1 is switched by the clock CLK. When the clock CLK is at high level, the switch S 1 is on such that the current source 204 provides a current Iref to charge the capacitor C 5 . When the clock CLK is at low level, the switch S 1 is off so as to stop charging the capacitor C 5 ; as a result, the low-frequency signal VC 5 increases in steps, as shown by the waveform 404 in FIG. 4 . During each clock period T CLK , the low-frequency signal VC 5 is increased by a difference

Δ VC 5 =Δt×I ref/ C 5,   [EQ-1]

where Δt is the duty cycle of the clock period T CLK . Once the low-frequency signal VC 5 reaches V 2 , as shown at time t 2 , the output COMP 3 of the comparator 208 becomes low, and enables the logic unit U 2 and disables the logic unit U 1 ; meanwhile, the non-inverting input of the comparator 208 is switched back to the voltage V 1 . During the logic unit U 1 is disabled, the switch S 1 remains off, and the switch S 2 is switched by the clock CLK. When the clock CLK is at high level, the switch S 2 is on such that the current source 206 discharges the capacitor C 5 , and when the clock CLK is at a low level, the switch S 2 is off so as to stop discharging the capacitor C 5 . As a result, the low-frequency signal VC 5 decreases in steps. During each clock period T CLK , the low-frequency signal VC 5 is decreased by a difference ΔVC 5 , as shown in the equation EQ-1. Because the duty cycle Δt of the clock period T CLK is less than the clock period T CLK , the low-frequency signal VC 5 has a much lower frequency than that of the voltage Vosc in the oscillator 214 , as shown by the waveform 404 in FIG. 4 . The period of the low-frequency signal VC 5 can be derived from the equation EQ-1 as

T _tri=[( V 2 −V 1)× C 5/(Δ t×I ref)]× T CLK ×2.   [EQ-2]

In this embodiment, the low-frequency signal VC 5 is a triangle wave, as shown by the waveform 404 in FIG. 4 . The modifying signal V_tri is generated by amplifying the low-frequency signal VC 5 by E 1 times by the amplifier 212 ; therefore, the modifying signal V_tri is also a triangle wave. Additionally, in this embodiment, the capacitor C 5 is charged and discharged in steps so the capacitance C 5 needs not be large.

Referring to FIGS. 3 and 4 . Since the signal VREF 2 has a fixed value and is combined with the modifying signal V_tri by the adder 300 to produce the upper limit VREF 3 of the hysteretic band, the upper limit VREF 3 is also a triangle wave, as shown by the waveform 400 in FIG. 4 . In the oscillator 214 of FIG. 3 , the currents IREF 1 and IREF 2 provided by the current sources 306 and 308 will determine the increasing and decreasing slopes of the voltage Vosc. When the voltage Vosc is lower than the lower limit VREF 1 of the hysteretic band, the output COMP 4 of the comparator 302 signals the flip-flop 310 to turn off the switch 54 to stop discharging the capacitor C 5 by the current IREF 2 , and turn on the switch S 3 to charge the capacitor C 5 by the current IREF 1 , thereby causing the voltage Vosc to increase. When the voltage Vosc is higher than the upper limit VREF 3 of the hysteretic band, the output COMP 5 of the comparator 304 signals the flip-flop 310 to turn off the switch S 3 to stop charging the capacitor C 5 by the current IREF 1 , and turn on the switch S 4 to discharge the capacitor C 5 by the current IREF 2 , thereby causing the voltage Vosc to decrease. As shown by the waveforms 400 and 402 in FIG. 4 , when the upper limit VREF 3 of the hysteretic band increases, the voltage Vosc will increase, and on the contrary, the voltage Vosc decreases. Referring to FIG. 3 , the period of the voltage Vosc is equal to the period T CLK of the clock CLK, and thus the period T CLK of the clock CLK will increase or decrease in accordance with the increase or decrease of the upper limit VREF 3 of the hysteretic band. In other words, the clock CLK will have a jitter frequency, thereby obtaining a jittering switching frequency for the power supply utilizing the clock CLK. The period of the clock CLK can be derived from the circuit of FIG. 3 as

In the above embodiment, although an adjustment on the upper limit of the hysteretic band is used for illustration, in other embodiments, an adjustment on the lower limit of the hysteretic band can be used alternatively, in order to modulate the hysteretic band.

FIG. 5 is another embodiment for the oscillator 214 shown in FIG. 2 , which employs voltage-controlled current sources 306 and 308 and further includes a current modifying circuit 500 to control the voltage-controlled current sources 306 and 308 , in addition to the adder 300 , comparators 302 and 304 , flip-flop 310 , and one shot circuit 312 . The current modifying circuit 500 has an error amplifier 502 for generating an error signal VEA depending on the difference between a reference voltage Vth and a feedback signal Vcomp proportional to the output voltage of the power supply, a clamp circuit 504 for clamping the maximum and minimum values of the error signal VEA to generate a clamped signal Vclamp, and an adder 506 for combining the clamped signal Vclamp and a reference signal VREF 4 to generate a current modifying signal Va for the voltage-controlled current sources 306 and 308 to modify the charging and discharging currents IREF 1 and IREF 2 . In this embodiment, when the currents IREF 1 and IREF 2 decrease such that the switching frequency of the power supply is lower than 20 KHz, there will be generated audible noise. However, the noise can also be fuzzed by the varied hysteretic band in a fixed range.

While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation to encompass all such modifications and similar arrangements.