Local input/output line precharge circuit of semiconductor memory device

1. Field of the Invention

The present invention generally relates to a local input/output line precharge circuit of a semiconductor memory device, and more specifically, to a technology of reducing current consumption by omitting a local input/output line precharge operation at a continuous write mode.

2. Description of the Related Art

Generally, a semiconductor memory device performs a precharge operation on a pair of local input/output lines at a read and write modes. That is, the pair of local input/output lines transmit a data signal between a pair of global input/output lines and an internal circuit. Here, the semiconductor memory device precharge the pair of local input/output lines at every read or write command, and then the accurate data signal can be transmitted.

FIG. 1 is a diagram illustrating the local input/output line precharge circuit of a conventional semiconductor memory device.

The conventional local input/output line precharge circuit comprises a precharge control unit 10 , an equalization unit 20 and a data output unit 30 .

The precharge control unit 10 which comprises inverters IV 1 and IV 2 drives a precharge signal LIO_RST to output a precharge control signal IOEQ.

The equalization unit 20 equalizes the pair of local input/output lines LIO and LIOb in response to the precharge control signal IOEQ. Here, the equalization unit 20 comprises NMOS transistors NM 1 ˜NM 3 which are controlled by the precharge control signal IOEQ. The NMOS transistors NM 1 and NM 2 have drains to receive a precharge voltage VBLP, and sources connected to the pair of local input/output lines LIO and LIOb, respectively. The NMOS transistor NM 3 , which has a drain and a source connected to the sources of the NMOS transistors NM 1 and NM 2 , equalizes the pair of local input/output lines LIO and LIOb.

The data output unit 30 outputs data signals of the pair of global input/output lines GIO and GIOb to the pair of local input/output lines LIO and LIOb in the write mode. Here, the data output unit 30 comprises a write driver control unit 31 , a global input/output line bar output unit 32 , a global input/output line output unit 33 , a pull-up driver 34 , a pull-down driver 35 , latch units 36 and 37 , a local input/output line driving unit 38 , and a local input/output line bar driving unit 39 .

The write driver control unit 31 comprises a NAND gate ND 1 and an inerter IV 3 .

The NAND gate ND 1 performs a NAND operation on a write driver enable signal BWEN and a write driver stop signal BAYBD. The inverter IV 3 inverts an output signal from the NAND gate ND 1 .

The global input/output line bar output unit 32 outputs a data signal of the global input/output line GIO in response to a data masking bar signal WDMb and an output signal BWEN 1 from the NAND gate ND 1 . Here, the global input/output line bar output unit 32 comprises a global input/output line bar driving unit 41 and a latch unit 42 .

The global input/output line bar driving unit 41 comprises PMOS transistors PM 1 and PM 2 that have drains to receive a power voltage VDD level in response to the data masking bar signal WDMb and a global input/output line bar signal GIOb respectively, and NMOS transistors NM 4 ˜NM 6 that are controlled by the global input/output line bar signal GIOb, the data masking bar signal WDMb and an output signal BWEN 1 from the NAND gate ND 1 respectively. The PMOS transistor PM 1 and the NMOS transistors NM 4 ˜NM 6 are connected serially between a power voltage terminal and a ground voltage terminal. The PMOS transistor PM 2 is connected between the power voltage terminal and the drain of the PMOS transistor PM 1 .

The latch unit 42 , which comprises inverter IV 4 and IV 5 whose output terminals are connected to their input terminals, maintains an output terminal of the global input/output line bar driving unit 41 at a predetermined level.

The global input/output line output unit 33 outputs the data signal BWEN 1 of the global input/output line GIO in response to the data masking bar signal WDMb and the output signal from the NAND gate ND 1 . Here, the global input/output line output unit 33 comprises PMOS transistors PM 3 and PM 4 that have drains to receive the power voltage VDD level in response to the data masking bar signal WDMb and the global input/output line signal GIO respectively, and NMOS transistors NM 7 ˜NM 9 that are controlled by the global input/output line signal GIO, the data masking bar signal WDMb and the output signal BWEN 1 from the NAND gate ND 1 respectively. The PMOS transistor PM 3 and the NMOS transistors NM 7 ˜NM 9 are connected serially between the power voltage terminal and the ground voltage terminal, and the PMOS transistor PM 4 is connected between the power voltage terminal and the drain of the PMOS transistor PM 3 .

The latch unit 44 , which comprises inverters IV 6 and IV 7 whose output terminals are connected to their input terminals, maintains an output terminal of the global input/output line driving unit 43 at a predetermined level.

The pull-up driver 34 comprises a PMOS transistor PM 5 , NMOS transistors NM 10 and NM 11 which are connected serially between the power voltage VDD terminal and the ground voltage terminal. Here, the PMOS transistor PM 5 applies a power voltage level to a node N 1 in response to an output signal from the inverter IV 1 , and the NMOS transistors NM 10 and NM 11 are connected serially between the node N 1 and the ground voltage terminal. The NMOS transistor NM 10 is controlled by an output signal BWEN 2 from the inverter IV 3 , and the NMOS transistor NM 11 is controlled by an output signal from the global input/output line bar output unit 32 , thereby applying a ground voltage level signal to the node N 1 .

The pull-down driver 35 comprises a PMOS transistor PM 6 and NMOS transistors NM 12 and NM 13 which are connected serially between the power voltage VDD terminal and the ground voltage terminal.

The PMOS transistor PM 6 applies the power voltage level to a node N 2 in response to the output signal from the inverter IV 1 , and the NMOS transistors NM 12 and NM 13 are connected serially between the node N 2 and the ground voltage terminal. The NMOS transistor NM 12 is controlled by the output signal BWEN 2 from the inverter IV 3 , and the NMOS transistor NM 13 is controlled by an output signal from the global input/output line output unit 33 , thereby applying the ground voltage level signal to the node N 2 .

The latch unit 36 which comprises inverters IV 8 and IV 9 maintains a potential of the node N 1 at a predetermined level, and the latch unit 37 which comprises inverters IV 10 and IV 11 maintains a potential of the node N 2 at a predetermined level.

The local input/output line driving unit 38 comprises an inverter IV 12 , a PMOS transistor PM 7 and a NMOS transistor NM 14 . Here, the inverter IV 12 inverts an output signal from the latch unit 37 , the PMOS transistor PM 7 applies a core voltage VCORE level to a node N 3 in response to an output signal from the inverter IV 12 , and the NMOS transistor N 14 applies the ground voltage level to the node N 3 in response to an output signal from the latch unit 36 .

The local input/output line bar driving unit 39 comprises an inverter IV 13 , a PMOS transistor PM 8 and a NMOS transistor NM 15 . Here, the inverter IV 13 inverts an output signal from the latch unit 36 , the PMOS transistor PM 8 applies the core voltage VCORE level to a node N 4 in response to an output signal from the inverter IV 13 , and the NMOS transistor NM 15 applies the ground voltage level to the node N 4 in response to an output signal from the latch unit 37 . The above-described conventional local input/output lines precharge circuit precharges a pair of local input/output lines at a predetermined level in the write and read modes, and then operates a write driver or input/output sense amplifier to transmit the data signal

However, although the write driver changes the levels of the pair of local input/output lines even when the pair of local input/output lines are not precharged, as shown in FIG. 2 , the write driver precharges the pair of local input/output lines at a continuous write mode, and loads data to precharge the pair of local input/output lines, repeatedly. As a result, the conventional circuit performs an unnecessary precharge operation at the continuous write mode, which results in increase of current consumption.

Accordingly, it is an object of the present invention to provide a local input/output line precharge circuit which does not perform an unnecessary precharge operation at a write mode of a semiconductor memory device, thereby preventing unnecessary current consumption.

In an embodiment, a local input/output line precharge circuit of a semiconductor memory device comprises a precharge control unit, an equalization unit and a data output unit. The precharge control unit outputs a precharge control signal to precharge a pair of local input/output lines in response to a continuous write signal activated when a write operation continues. The equalization unit precharges and equalizing the pair of local input/output lines in response to the precharge control signal. The data output unit outputs data signals of a pair of global input/output lines to the pair of local input/output lines in response to output signal from the equalization unit.

Other aspects and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:

FIG. 1 is a diagram illustrating a local input/output line precharge circuit of a conventional semiconductor memory device;

FIG. 2 is a diagram illustrating input/output waveforms of the local input/output line precharge circuit of FIG. 1 ;

FIG. 3 is a diagram illustrating a local input/output line precharge circuit of a semiconductor memory device according to an embodiment of the present invention; and

FIG. 4 is a diagram illustrating input/output waveforms of the local input/output line precharge circuit of FIG. 3 .

The present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a diagram illustrating a local input/output line precharge circuit of a semiconductor memory device according to an embodiment of the present invention.

In an embodiment, a local input/output line precharge circuit of a semiconductor memory device comprises a precharge control unit 100 , an equalization unit 200 and a data output unit 300 .

The precharge control unit 100 comprises an OR gate OR, and inverters IV 14 and IV 15 .

The OR gate OR performs an OR operation on a precharge signal LIO_RST and a continuous write signal WR 12 BWEN. The inverter IV 15 inverts an output signal from the OR gate OR to output a precharge control signal IOEQ, and the inverter IV 14 inverts the precharge signal LIO_RST. Here, the precharge signal LIO_RST is enabled to a high level at a precharge mode, and the continuous write signal WR 12 BWEN is enabled to a high level when a write command is continued.

The equalization unit 200 equalizes a pair of local input/output lines LIO and LIOb in response to the precharge control signal IOEQ. Here, the equalization unit 200 comprises NMOS transistors which are controlled by the precharge control signal IOEQ. The NMOS transistors NM 16 and NM 17 have drains to receive the precharge voltage VBLP and sources connected to the pair of local input/output lines LIO and LIOb, respectively. The NMOS transistor NM 18 has a drain and a source connected to the sources of the NMOS transistors NM 16 and NM 17 respectively, thereby equalizing the pair of local input/output lines LIO and LIOb.

The data output unit 300 outputs data signals of a pair of global input/output lines GIO and GIOb to the pair of local input/output lines LIO and LIOb at a write mode. Here, the data output unit 300 comprises a write driver control unit 400 , a local input/output line output unit 500 and a local input/output line bar output unit 600 .

The write driver control unit 400 comprises a NAND gate ND 2 and an inverter IV 16 . The NAND gate ND 2 performs a NAND operation on a write driver enable signal BWEN and a write driver stop signal BAYBD. The inverter IV 16 inverts an output signal BWEN 1 from the NAND gate ND 2 .

The write driver enable signal BWEN is a signal to drive drivers 520 and 620 , and the write driver stop signal BAYBD is a signal to stop the operations of the drivers 520 and 620 .

The local input/output line output unit 500 comprises a global input/output line bar output unit 510 , a pull-up driver 520 , a latch unit 530 and a local input/output line driving unit 540 .

The global input/output line bar output unit 510 outputs the data signal of the global input/output line bar GIOb in response to a data masking bar signal WDMb, a global input/output line bar signal GIOb and the output signal BWEN 1 from the NAND gate ND 2 . Here, the global input/output line bar output unit 510 comprises a global input/output line bar driving unit 511 and a latch unit 512 . The data masking bar signal WDMb for masking the data signal does not transmit the inputted data of the pair of global input/output lines to the pair of local input/output lines when the data masking bar signal WDMb is enabled to ‘high’, so that the write operation may not be performed.

The global input/output line bar driving unit 511 comprises PMOS transistors PM 9 and PM 10 that have drains to receive a power voltage VDD level in response to the data masking bar signal WDMb and the global input/output line bar signal GIOb, and NMOS transistors NM 19 ˜NM 21 which are controlled by the global input/output line bar signal GIOb, the data masking bar signal WDMb and an output signal BWEN 1 from the NAND gate ND 2 . The PMOS transistor PM 9 and the NMOS transistors N 19 ˜NM 21 are connected serially between a power voltage terminal and a ground voltage terminal. The PMOS transistor PM 10 is connected between the power voltage terminal and the drain of the PMOS transistor PM 9 .

The latch unit 512 , which comprises inverters IV 17 and IV 18 whose output terminals are connected to their input terminals, maintains an output terminal of the global input/output line bar driving unit 511 at a predetermined level.

The pull-up driver 520 comprises a PMOS transistor PM 13 , NMOS transistors NM 25 and NM 26 which are connected serially between the power voltage VDD terminal and the ground voltage terminal. Here, the PMOS transistor PM 13 applies a power voltage level to a node N 5 in response to an output signal from the inverter IV 14 , and the NMOS transistors NM 25 and NM 26 are connected serially between the node N 5 and the ground voltage terminal. The NMOS transistor NM 25 is controlled by an output signal BWEN 2 from the inverter IV 16 , and the NMOS transistor NM 26 is controlled by an output signal from the global input/output line bar output unit 510 , thereby applying the ground voltage level signal to the node N 5 .

The latch unit 530 which comprises IV 21 and IV 22 maintains a potential of the node N 5 at a predetermined level. An output terminal of the inverter IV 21 is connected to an input terminal of the inverter IV 22 , and an output terminal of the inverter IV 22 is connected to an input terminal of the inverter IV 21 .

The local input/output line driving unit 540 comprises a PMOS transistor PM 15 and a NMOS transistor NM 29 which are connected serially between the power voltage terminal and the ground voltage terminal. Here, the inverter IV 25 inverts an output signal from the latch unit 630 , the PMOS transistor PM 15 applies a core voltage VCORE level to a node N 7 in response to an output signal PUA from the inverter IV 25 , and the NMOS transistor N 29 applies the ground voltage level to the node N 7 in response to an output signal from the latch unit 530 .

The local input/output line bar output unit 600 comprises a global input/output line output unit 610 , a pull-down driver 620 , a latch unit 630 and a local input/output line bar driving unit 640 .

The global input/output line output unit 610 outputs the data signal of the global input/output line GIO in response to the data masking bar signal WDMb, the global input/output line signal GIO and the output signal BWEN 1 from the NAND gate ND 2 .

The global input/output line driving unit 611 comprises PMOS transistors PM 11 and PM 12 that have drains to receive the power voltage VDD level in response to the data masking bar signal WDMb, and the global input/output line signal GIO, and NMOS transistors NM 22 ˜NM 24 which are controlled by the global input/output line signal GIO, the data masking bar signal WDMb and the output signal BWEN 1 from the NAND gate signal ND 2 . The PMOS transistor PM 11 and the NMOS transistors NM 22 ˜NM 24 are connected serially between the power voltage terminal and the ground voltage, and the PMOS transistor PM 12 is connected between the power voltage terminal and the drain of the PMOS transistor PM 11 .

The latch unit 612 , which comprises inverters IV 19 and IV 20 whose output terminals are connected to their input terminals, maintains an output terminal of the global input/output line driving unit 611 at a predetermined level.

The pull-down driver 620 comprises a PMOS transistor PM 14 , NMOS transistors NM 27 and NM 28 which are connected serially between the power voltage VDD terminal and the ground voltage terminal. Here, the PMOS transistor PM 14 applies the power voltage level to a node N 6 in response the output signal from the inverter IV 14 , and the NMOS transistors NM 27 and NM 28 are connected serially between the node N 6 and the ground voltage terminal. The NMOS transistor NM 27 is controlled by the output signal BWEN 2 from the inverter IV 16 , and the NMOS transistor NM 28 is controlled by an output signal from the global input/output line output unit 610 .

The latch unit 630 which comprises inverters IV 23 and IV 24 maintains a potential of the node N 6 at a predetermined level. An output terminal of the inverter IV 23 is connected to an input terminal of the inverter IV 24 , and an output terminal of the inverter IV 24 is connected to an input terminal of the inverter IV 23 .

The local input/output line bar driving unit 640 comprises an inverter IV 26 , a PMOS transistor PM 16 and a NMOS transistor NM 30 . Here, the inverter IV 26 inverts an output signal from the latch unit 530 , the PMOS transistor PM 16 applies the core voltage VCORE level to a node N 8 in response to an output signal PUB from the inverter IV 26 , and the NMOS transistor NM 30 applies the ground voltage level to the node N 8 in response to an output signal from the latch unit 630 .

FIG. 4 is a diagram illustrating input/output waveforms of the local input/output line precharge circuit of FIG. 3 .

The data output unit 300 outputs the data signals of the pair of the global input/output lines GIO and GIOb to the pair of local input/output lines LIO and LIOb.

As shown in FIG. 4 , when a read command RD is applied after a write command WT is applied three times successively, the continuous write signal WT 12 BWEN is enabled to ‘high’ while the write operation is performed.

The precharge control unit 100 outputs the precharge control signal IOEQ having a high level for driving the equalization unit 200 only when the continuous write signal WR 12 BWEN and the precharge signal LIO_RST are all ‘low’, and the precharge control signal IOEQ having a low level since the continuous write signal WR 12 BWEN is continuously ‘high’ at the write mode.

Thereafter, the equalization unit 200 precharges the pair of the local input/output lines LIO and LIOb at a level of the precharge voltage VBLP when the precharge control signal IOEQ is ‘high’, and outputs a data signal of the data output unit 300 to the pair of local input/output lines LIO and LIOb when the precharge control signal IOEQ is ‘low’.

In this way, the local input/output line precharge circuit according to the embodiment of the present invention outputs the precharge control signal IOEQ having the low level at the continuous write mode to perform the write operation without a precharge operation, and outputs the precharge control signal IOEQ having the high level at the read mode to perform the precharge operation.

The above precharge operation can be performed due to a sufficient driving capacity for changing the pair of local input/output lines at a desired level even when a write driver (not shown) does not precharge the pair of local input/output lines.

Accordingly, in a local input/output line precharge circuit according to an embodiment of the present invention, current consumption can be reduced by omitting a precharge operation at a continuous write mode of a semiconductor memory device.

While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that the invention is not limited to the particular forms disclosed. Rather, the invention covers all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined in the appended claims.