A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.

Claims

6 · 3 independent · depth 2

6 granted claims

›1.independentA method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences…+1

›3.independentA method for use by a host microprocessor which translates sequences of target instructions from a target instruction set for a target processor to se…+1

›5.independentA method of executing instructions in a host microprocessor which translates sequences of instructions from a target instruction set for a target proc…+1

Classifications

7 codes

IPC · International Patent Classification

Section G — Physics

G06F009/45

USPC · US Patent Classification

717/138712/227703/26712/209703/27712/228

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Pendency

5.4 y

1,987 days filing → grant

Office actions

non-final + final

Responses

2 RCE

Examiner

Richard L. Ellis

art unit 2183 · TC 2100

Law firm

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Citations: 6 back · 0 forward

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