Single chip color CMOS image sensor with two or more line reading structure

This is a continuation-in-part of prior application Ser. No. 08/642,537, filed on May 3, 1996, U.S. Pat. No. 5,901,257, the benefit of the filing date of which is hereby claimed under 35 U.S.C. § 120.

The present invention relates to metal oxide semiconductor (MOS) image sensors and, more particularly, a single chip CMOS image sensor having a novel two or more line reading structure and an improved color filter pattern.

Integrated circuit technology has revolutionized various fields including computers, control systems, telecommunications, and imaging. In the field of imaging, the charge coupled device (CCD) sensor has made possible the manufacture of relatively low cost and small hand-held video cameras. Nevertheless, the solid-state CCD integrated circuits needed for imaging are relatively difficult to manufacture, and therefore are expensive. In addition, because of the differing processes involved in the manufacture of CCD integrated circuits relative to MOS integrated circuits, the signal processing portion of the imaging sensor has typically been located on a separate integrated chip. Thus, a CCD imaging device includes at least two integrated circuits: one for the CCD sensor and one for the signal processing logic.

Some of the further drawbacks of CCD technology are discussed in “Active Pixel Sensors—Are CCD's Dinosaurs?” by E. R. Fossum, Proceedings of the SPIE—The International Society for Optical Engineering, Vol. 1900, 1993, pp. 2-14. As stated therein, “[a]lthough CCDs have become a technology of choice for present-day implementation of imaging and spectroscopic instruments due to their high sensitivity, high quantum efficiency, and large format, it is well-known that they are a particularly difficult technology to master. The need for near-perfect charge transfer efficiency makes CCDs (1) radiation “soft,” (2) difficult to reproducibly manufacture in large array sizes, (3) incompatible with the on-chip electronics integration requirements of miniature instruments, (4) difficult to extend the spectral responsivity range through the use of alternative materials, and (5) limited in their readout rate.”

An alternative low cost technology to CCD integrated circuits is the metal oxide semiconductor (MOS), integrated circuit. Not only are imaging devices using MOS technology less expensive to manufacture relative the CCD imaging devices, for certain applications MOS devices are superior in performance. For example, the pixel elements in a MOS device can be made smaller and therefore provide a higher resolution than CCD image sensors. In addition, the signal processing logic necessary can be integrated alongside the imaging circuitry, thus allowing for a single integrated chip to form a complete stand alone imaging device.

Examples of MOS imaging devices are detailed in “A ¼ Inch Format 250K Pixel Amplified MOS Image Sensor Using CMOS Process” by Kawashima et al., IEDM 93-575 (1993), and “A Low Noise Line-Amplified MOS Imaging Devices” by Ozaki et al., IEEE Transactions on Electron Devices, Vol. 38, No. 5, May 1991. In addition, U.S. Pat. No. 5,345,266 to Denyer titled “Matrix Array Image Sensor Chip” describes a MOS image sensor. The devices disclosed in these publications provide a general design approach to MOS imaging devices. In addition, MOS approaches to color imaging devices are described in “Color Filters and Processing Alternatives for One-Chip Cameras”, by Parulski, IEEE Transactions on Electron Devices, Vol. ED-32, No. 8, August 1985, and “Single-Chip Color Cameras With Reduced Aliasing” by Imaide et al., Journal of Imaging Technology, Vol. 12, No. 5, October 1986, pp. 258-260.

In the MOS solid-state color image sensors, a complementary color filter pattern is often used. Arrays of pixels may be made to detect color by being covered with a regular pattern of color filter patches, known as a color filter pattern. The filter patches can be fabricated directly on the sensor or on a transparent substrate which is later cemented to the chip. Color filter patterns may include colors such as red (R), green (G), blue (B), yellow (Ye), cyan (Cy) and magenta (Mg). The pixels beneath the color filter pattern emit signals when they are exposed to the type of light indicated by the color filter patch. Thus, a red signal could be obtained from a pixel beneath a red filter patch, a blue signal could come from a pixel beneath a blue filter patch, and so on.

However, some image sensors do not obtain the standard red, green and blue signals from red, green and blue filtered pixels. Instead, they use combinations of other colors to obtain the standard ones. For example, red (R) can be formed according to the equation R=(W+Ye)−(G+Cy), where the color filter pixel signals are W=white, Ye=yellow, G=green, and Cy=cyan. In cases such as this, the four pixel signals being processed are obtained from a 2×2 block of one of each type of pixel sensors, rather than a 1×4 row of pixel sensors which would tend to distort the color image. The 2×2 block presents a problem for standard pixel scanning methods because standard methods scan each row, one at a time. In contrast, the 2×2 block of pixels comes from sections of two separate rows. Thus, the system cannot process the data as it scans each row. It must wait until the next row is also scanned to obtain the remaining information which it needs, and it must somehow save the data from the previous row until it does so.

Just as the color signals in such cases can be a combination of the signals from a 2×2 pixel block, the chrominance signal, which correlates to the color of the image, is also sometimes obtained from a combination of signals from pixels in two separate rows. In fact, this is the case for the chrominance signal in many systems, even those in which R, G and B filters are used to obtain the color signals directly. Therefore, it is required in such systems to somehow have the data from two separate rows available at the same time so that the required combinations can be processed. In most prior art devices, an external one-line delay line (e.g. a CCD delay line) is used for this purpose. The delay line scans in one row and holds the data until the next row can be scanned to provide the needed information.

In the movement from CCD to MOS based implementations, methods of implementing the circuitry have been sought which can easily be fabricated on a single MOS chip. The approach of using an external delay line device in the MOS color image sensors, which was carried over from the old CCD technology, has inherently required the use of components which are external to the MOS circuit and which are sometimes required to be on a separate chip, in addition to increasing the relative complexity of the implementation. It is a general principle that power consumption and cost would decrease if the number of chips and complex components necessary to accomplish the task were decreased. The present invention is directed towards a solution which provides the needed data from two rows of pixels at the same time, without using an external delay line device, and which can be integrated on a single chip with the MOS sensor array.

In addition, the color filter patterns used in the prior art MOS color image sensors, from which the needed data is obtained, are also often not optimized. Any color can be thought of as a mixture of the three primary colors: red, blue, and green. However, as is known in the art, humans do not process red, green, and blue equally. Rather, humans rely upon the three primary colors in approximate accordance with: 0.6Green+0.3Red+0.1Blue. Thus, to the human eye, green is the most important color, red is the next most important, and blue is the least most important. Based upon this knowledge, the pixel array should have a color filter pattern (also referred to as a color coding scheme) that is more heavily weighted along the lines of green than red or blue. Prior art color coding schemes have attempted to achieve this in various ways.

The prior art has shown that checkerboard patterns are superior to linear ones. One of the most common schemes uses a matrix in which every other pixel is green (G), and the remaining pixels form a checkerboard pattern of alternating red (R) and blue (B). Another pattern uses a checkerboard pattern of equal amounts of cyan (Cy), yellow (Ye), white (W) and green (G). A noted advantage of using the colors cyan, yellow and green is that since green is formed by overlapping yellow and cyan, only two filter fabrication mask steps are needed, as opposed to the three needed for a RGB filter. The present invention discloses a different color filter pattern, using green, yellow and cyan, which is optimized for sensitivity.

The present invention is directed to a single chip color MOS image sensor with a novel two-line reading structure which allows the simultaneous reading of line signals from two adjacent rows of pixels so that combinations of signals from pixels in adjacent rows may be obtained without the use of an external delay line device. The sensor includes a pixel array having superimposed thereon an improved color filter pattern, a two-line reading structure with a first set of storage capacitors, a first set of switches for selectively placing signals from a first row of the pixel array on the first set of storage capacitors, a second set of storage capacitors, a second set of switches for selectively placing signals from a row adjacent to said first row of the pixel array on the second set of storage capacitors, and at least a third and fourth set of switches for selectively reading out said signals from the storage capacitors on output lines as a set of line signals. The two-line reading structure may be repeated so as to provide four line signals. The capacitors, MOS switches and amplifiers of the reading structure are easily fabricated as part of a MOS image sensor on a single chip. Also, the improved color filter pattern of the device, which includes green, yellow and cyan, requires only two filter fabrication mask steps, and is designed for optimal sensitivity.

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a block diagram of a single-chip CMOS imaging sensor formed in accordance with the present invention;

FIG. 2 is a schematic diagram of a simplified single-column two-line pixel reading structure formed in accordance with the present invention and shown for purposes of illustration;

FIG. 3 is a timing diagram illustrating the operation of the single-column two-line pixel reading structure shown in FIG. 2;

FIG. 4A is a diagram of a prior art color filter pattern that may be used in the preferred embodiment of the invention;

FIG. 4B is a diagram of a second prior art color filter pattern;

FIG. 4C is a diagram of an inventive color filter pattern;

FIGS. 5A and 5B are schematic diagrams of a six-column, four-reading channel, non-interlace reading structure formed in accordance with the present invention;

FIG. 6 is a timing diagram illustrating the operation of the reading structure shown in FIG. 5B;

FIGS. 7A and 7B are schematic diagrams of a six-column, four reading channel, interlace reading structure formed in accordance with the present invention;

FIG. 8A is a timing diagram illustrating the operation of the reading structure of FIG. 7B for an even field reading operation;

FIG. 8B is a timing diagram illustrating the operation of the reading structure of FIG. 7B for an odd field reading operation;

FIG. 9 is a timing diagram illustrating the overall timing of the even and odd field reading operations of FIGS. 8A and 8B for one frame of TV timing;

FIG. 10 is a schematic diagram of a six-column, two reading channel, interlace reading structure formed in accordance with the present invention;

FIG. 11A is a timing diagram illustrating the operation of the reading structure of FIG. 10 for an even field reading operation; and

FIG. 11B is a timing diagram illustrating the operation of the reading structure of FIG. 10 for an odd field reading operation.

With reference to FIG. 1, a block diagram of a single-chip CMOS imaging sensor includes an image sensor array 101 . The retrieval of information from the image sensor array is done by the peripheral circuitry of FIG. 1 and the output is done in accordance with the well known NTSC scheme. This scheme allows the output signals from the circuit to be transmitted and displayed by conventional means.

The signals from the sensor array 101 are processed by a sensor reading structure 201 , which is formed in accordance with the present invention. As will be later explained, this novel reading structure allows the reading of two line signals from two separate rows of pixels simultaneously, without the use of an external delay line device. The sensor reading structure 201 outputs line signals SIG 1 , SIG 2 , SIG 3 and SIG 4 , which are amplified by signal amplifiers 305 . In one actual embodiment, the signal amplifiers 305 are formed in accordance with co-pending application Ser. No. 08/538,441 entitled “IMPROVED CHARGE AMPLIFIER FOR MOS IMAGING ARRAY AND METHOD OF MAKING SAME” to Shyu et al. filed Oct. 3, 1995, and co-pending application Ser. No. 08/617,313 entitled “IMPROVED CHARGE AMPLIFIER FOR MOS IMAGING ARRAY AND METHOD OF MAKING SAME” to Shyu et al. filed Mar. 18, 1996, and both herein incorporated by reference.

Amplified line signals SIG 1 ′, SIG 2 ′, SIG 3 ′ and SIG 4 ′ from the signal amplifiers 305 are then processed by processor 307 which performs automatic gain control amplification and black level calibration. The black level calibration attempts to eliminate the portion of the signal which exists when no light is being detected, as is known in the art, thus allowing for a truer zero reference signal so that the later signal processing is improved. The automatic gain control amplifiers (AGC) amplify the signals at a controlled level for further processing.

Processed line signals SIG 1 ″ to SIG 4 ″ from processor 307 go to the color matrix 309 . The color matrix 309 combines the line signals in various proportions according to matrix equations and also performs gamma correction so as to derive the output color signals, such as green (G′), red (R′), blue (B′), or the luminance signal (Y′). The “prime” indicates the signal has undergone gamma correction. The red (R′) and blue (B′) output color signals may be obtained as a function of the difference between two line signals, as will be explained later in more detail. The luminance signal (Y′) is formed from a linear matrix function by which the other signals are combined in various proportions. The processor 311 , which performs the luminance signal process, takes the signal Y′ from the color matrix 309 and outputs the signal YH along with a feedback signal which goes to the AEC detector 317 . The YH signal is the luminance signal with high frequency components.

The color signals G′, R′ and B′ go from the color matrix 309 to the processor 313 , which performs the chromaticity signal process, where they are processed so as to produce the signals −(R−Y) and −(B−Y), from which the chroma signal is formed. The chroma signal is formed by quadrature modulating the two color difference signals, (R−Y) and (B−Y), on a color subcarrier. In alternate systems, I (in phase) and Q (quadrature) color difference signals are sometimes used rather than (R−Y) and (B−Y), although the latter are what are most often used in consumer cameras. The phase and amplitude of the chroma signal indicate hue and saturation.

The NTSC encoder 315 receives control timing signals SYNC and BLANK from a video timing generator 319 , and also receives control signals FSC, HUE and SATURATION. The YH signal from the luminance signal process 311 , and the color difference signals −(R−Y) and −(B−Y) from the chromaticity signal process 313 , go to the NTSC encoder 315 where they are processed to produce the output signals CVBS (composite video with blank and sync) and the Y+C combined signal. The baseband luminance signal (Y) correlates to the brightness of the image, and the quadrature-modulated chrominance signal (C) correlates to the color of the image.

The processor 311 , which performs the luminance signal process, outputs a feedback signal to the AEC detector 317 , which outputs a control signal to the controller 321 which performs the AEC & AGC control. As is known in the art, AEC refers to automatic exposure control. The video timing generator 319 outputs timing signals SAMPLE and PRECHARGE which go to the sample and precharge areas of the array row controller 151 , respectively, for purposes of controlling the scanning of the image sensor array 101 . The array row controller 151 also includes a row driver section. The video timing generator 319 also outputs a timing signal to the controller 321 which performs the AEC & AGC control. The controller 321 outputs control signals to the sample timing counter 323 and to the precharge timing counter 325 . The sample timing counter 323 and the precharge timing counter 325 are connected to the sample and precharge areas of the array row controller 151 , respectively. The image sensor array 101 is controlled by the array row controller 151 , the row calibration cells 153 , and the column calibration cells 155 .

As noted above, it is desirable that the sensor reading structure 201 be able to read two line signals from two separate rows in such a way that the needed portions of data from both rows is available to be processed at the appropriate time. Prior art devices have used delay lines for this purpose, where, for example, one row of pixels would be scanned into the delay line and held for a time necessary until the second row could be scanned. The problem with this approach is that the delay line is often external to the MOS imaging sensor, which can add to the number of chips and the complexity of the implementation. Thus, there is a need for a structure which can be easily fabricated on the same chip as the MOS sensor array and which can make available the needed signals from two separate rows of pixels during a specified processing interval.

Turning now to FIG. 2, a simplified single-column two-line sensor pixel reading structure 201 formed in accordance with the present invention is shown for purposes of illustration. This structure illustrates the method by which the present invention may read two line signals from two rows of pixels simultaneously and thus provide the needed portions of data from the two rows during the specified processing interval. As will be seen below, the structure of FIG. 2 forms the building block of an arbitrarily large image sensor array.

The sensor reading structure 201 reads a pixel sensor array 101 which includes a single column of pixels 103 , designated as pixels 103 A, 103 B, 103 C and 103 D. The pixels 103 A to 103 D are controlled by pixel control signals P 1 , P 2 , P 3 and P 4 , respectively. In a color image sensor, each pixel is covered by a color filter patch. The signals from the pixels 103 A to 103 D are alternately amplified by a signal amplifier 205 . The signal amplifier 205 may be formed in accordance with co-pending application Ser. No. 08/538,441 entitled “IMPROVED CHARGE AMPLIFIER FOR MOS IMAGING ARRAY AND METHOD OF MAKING SAME” to Shyu et al. filed Oct. 3, 1995, and co-pending application Ser. No. 08/617,313 entitled “IMPROVED CHARGE AMPLIFIER FOR MOS IMAGING ARRAY AND METHOD OF MAKING SAME” to Shyu et al. filed Mar. 18, 1996.

The amplified pixel signals are temporarily stored on capacitors C 1 , C 2 , C 3 and C 4 . The placement of the amplified pixel signals on the four capacitors is controlled by sets of switches SW 1 and SW 2 . Switch SW 1 places signals on capacitors C 1 and C 2 , and switch SW 2 places signals on capacitors C 3 and C 4 . The stored pixel signals on the capacitors C 1 to C 4 are transferred to line signals SIG 1 and SIG 2 by two sets of output switches SW 3 and SW 4 . Switch set SW 3 places signals from capacitor C 1 on line signal SIG 1 and from capacitor C 3 on line signal SIG 2 . Switch set SW 4 places signals from capacitor C 2 on line signal SIG 1 and from capacitor C 4 on line signal SIG 2 . Line signals SIG 1 and SIG 2 are further amplified by signal amplifiers 305 and become amplified line signals SIG 1 ′ and SIG 2 ′. It should be noted that in the preferred embodiment, capacitors are used to store the amplified pixel signals. However, it can be appreciated that any type of memory cells may be used to store the signal. Indeed, most types of memory cells, such as DRAMs, SRAMs, and EEPROMs include therein a capacitor or capacitor-like device. Thus, the term capacitor as used herein shall mean any type of memory cell that can be used to store a signal.

In different embodiments, the pixels 103 A, 103 B, 103 C, and 103 D may be either passive pixels or active pixels. For passive pixels, amplifier 205 would generally be a charge amplifier, and amplifiers 305 could also be charge amplifiers. However, if pixels 103 A, 103 B, 103 C, and 103 D were active pixels, amplifier 205 could be made to be a voltage buffer or voltage amplifier, or could be left out of the circuit altogether. In addition, as illustrated in FIG. 2, sample buffers 207 are shown to be coupled between the capacitors C 1 , C 2 , C 3 , and C 4 and the amplifiers 305 . The sample buffers 207 output a voltage rather than a charge, thus allowing the amplifiers 305 to be voltage amplifiers rather than charge amplifiers. In an embodiment where sample buffers 207 were not included, amplifiers 305 would generally be charge amplifiers.

The goal of the circuit in FIG. 2 is to simultaneously place on the line signals SIG 1 and SIG 2 signals from two pixels from adjacent rows. For example, pixel 103 A will first be simultaneously read with pixel 103 B, then pixel 103 B will be simultaneously read with pixel 103 C, and finally pixel 103 C will be simultaneously read with pixel 103 D. These simultaneous readings are accomplished by storing the signal from each pixel on two capacitors. Two capacitors are needed for each signal since each pixel signal (with the exception of the first and last pixel in the column) is read twice. For example, pixel 103 B is simultaneously read with pixel 103 A and then with pixel 103 C.

The operation of the circuit in FIG. 2 is illustrated by the timing diagrams shown in FIG. 3 . As shown in FIG. 3, at the beginning of time period 1 , the pixel control signal P 1 goes high at the same time as switch set SW 1 . This causes the signal from pixel 103 A to be amplified by signal amplifier 205 and stored on capacitors C 1 and C 2 . Thus, the signal from pixel 103 A is stored on two capacitors, and these two stored signals are referenced as stored pixel signal 103 A′ on capacitor C 1 , and stored pixel signal 103 A″ on capacitor C 2 . While the timing diagrams of FIG. 3 show these signals as being transferred instantaneously, it is understood that the actual transfer of these signals involves transient periods, due to the charging of the capacitors and similar phenomena, which are not shown in the diagrams. After pixel signal 103 A′ and pixel signal 103 A″ are stored, then output switch set SW 3 goes high which causes stored pixel signal 103 A′ to be transferred from capacitor C 1 to line signal SIG 1 . Although the timing diagrams for line signals SIG 1 and SIG 2 show the names of the pixel signals which are transferred to the line signals after the output switch sets SW 3 or SW 4 are activated, it is understood that the named signals do not necessarily remain on the line signals for the full time period shown in the diagram, and are shown there only for purposes of illustration as if the charge from each of the capacitors had been transferred to each of the line signals. Line signal SIG 1 and line signal SIG 2 are obtained simultaneously, although during time period 1 , line signal SIG 2 has not been shown to be charged with a signal.

At the beginning of time period 2 , the pixel control signal P 2 goes high at the same time as switch set SW 2 . This causes the signal from pixel 103 B to be stored on capacitors C 3 and C 4 , and these two stored signals are referenced as stored pixel signal 103 B′ and stored pixel signal 103 B″, respectively. Next, output switch set SW 4 goes high which causes stored pixel signal 103 B″ to be transferred from capacitor C 4 to line signal SIG 2 , and also simultaneously causes the stored pixel signal 103 A″, which was stored during time period 1 , to be transferred from capacitor C 2 to line signal SIG 1 . Thus, at the point during time period 2 when SW 4 goes high, the line signals SIG 1 and SIG 2 contain the signals from pixels 103 A and 103 B, respectively, which are in adjacent rows, as is the goal of the system.

At the beginning of time period 3 , the pixel control signal P 3 goes high at the same time as switch set SW 1 . This causes the signal from pixel 103 C to be stored on capacitors C 1 and C 2 , and these two stored signals are referenced as stored pixel signal 103 C′ and stored pixel signal 103 C″, respectively. Next, output switch set SW 3 goes high which causes stored pixel signal 103 C′ to be transferred from capacitor C 1 to line signal SIG 1 , and also simultaneously causes the stored pixel signal 103 B′, which was stored during time period 2 , to be transferred from capacitor C 3 to line signal SIG 2 . Thus, at the point during time period 3 when SW 3 goes high, the line signals SIG 1 and SIG 2 contain the signals from pixels 103 C and 103 B, respectively, which are in adjacent rows, as is the goal of the system.

During time period 4 , the process repeats as it did during time period 2 , so as to cause the line signals SIG 1 and SIG 2 to contain the signals from pixels 103 C and 103 D, respectively, which are in adjacent rows, as is the goal of the system. The process of FIG. 3 is repeated until all of the rows of the pixel array have been processed.

Turning now to FIG. 4A, a prior art color filter pattern is shown. This prior art color coding scheme is one of the most common and uses a half green (G) pattern, checkerboarded with red (R) and blue (B). The color filter pattern of FIG. 4A may be used in the preferred embodiment of the invention. FIG. 4B shows another prior art color coding scheme which uses equal amounts of cyan (Cy), yellow (Ye), white (W) and green (G), with the advantage that since green is formed by overlapping yellow and cyan, only two filter fabrication steps are needed as opposed to the three needed for a RGB filter. In FIG. 4B, the color red (R) may be derived according to the equation R=(W+Ye)−(G+Cy), and blue (B) may be derived from B=(W+Cy)−(Ye+G).

In contrast, FIG. 4C shows an inventive color coding scheme of the present invention which uses the same proportion of green (G) components as the prior art color coding scheme of FIG. 4A, but uses yellow (Y) and cyan (Cy) to fill in the remainder rather than red (R) and blue (B). Similar to the prior art color coding scheme of FIG. 4B, in regard to the filter fabrication mask steps, green is formed by overlapping yellow and cyan, thus requiring only two filter fabrication mask steps.

Further, if the color filter has ideal spectral characteristics, then the color yellow can be the combination of green and red. Similarly, cyan can be the combination of green and blue. The specific equations used by the preferred embodiment for the color coding scheme of FIG. 4C are Ye=Godd+αR (where Ye is yellow pixels, Godd is green pixels next to the yellow pixels which are all in odd numbered rows, R is red and α is a constant), and Cy=Geven+βB (where Cy is cyan pixels, Geven is green pixels next to the cyan pixels which are all in even numbered rows, B is blue and β is a constant) and G=Godd/2+Geven/2. Solving the first equation for R yields: R=(Ye−Godd)/α, and solving the second equation for B yields: B=(Cy−Geven)/β. Also, with regard to the spatial frequency components, the equations which are used are: for the Y-channel, Fx=1/δx; Fy=1/δy, and for the C-channel, Fx=½δx; Fy=½δy, where δx is the width of a pixel component and δy is the length of a pixel component.

With reference to FIGS. 5 A and SB, a six-column two-line non-interlace (progressive scan) reading structure 201 is formed in accordance with the present invention and includes six columns of four rows of pixels 103 . Any of the color coding schemes of FIGS. 4A, 4 B, or 4 C, or others, may be used. As shown, each pixel in each block of four pixels in FIG. 5A is designated as having one of four colors, CLR 1 , CLR 2 , CLR 3 or CLR 4 . In the color coding scheme of FIG. 4A, colors CLR 1 and CLR 4 would be the same (green), while in the color coding scheme of FIG. 4C, colors CLR 2 and CLR 3 would be the same (green).

In the embodiment illustrated in FIG. 5B, the two-line reading structure is doubled so as to provide four reading channel line signals. The first column of pixels has pixels 103 A to 103 D, the second column has pixels 103 E to 103 H, and so on until the sixth column which has pixels 103 U to 103 X. Each row of pixels is controlled by a pixel control signal P 1 , P 2 , P 3 or P 4 . All of the pixels in the first row, including pixels 103 A, 103 E, 103 I, 103 M, 103 Q and 103 U, are controlled by pixel control signal P 1 . The pixels in the second, third and fourth rows are similarly controlled by pixel control signals P 2 , P 3 and P 4 , respectively.

The signals from the pixels in each of the six columns of pixels are alternately amplified by six signal amplifiers 205 . As described previously with reference to FIG. 2, signal amplifiers 205 may be charge amplifiers or voltage amplifiers, and the pixels may be active or passive, and there may also be sample buffers inserted after the capacitors. The amplified pixel signals are temporarily stored on twenty-four capacitors C 1 to C 24 , four for each column, including capacitors C 1 to C 4 for the first column, capacitors C 5 to C 8 for the second column, and so on until the sixth column where the signals are stored on capacitors C 21 to C 24 . The placement of the amplified pixel signals on the twenty-four capacitors is controlled by two sets of switches SW 1 and SW 2 . The stored pixel signals on the capacitors C 1 to C 24 are transferred to line signals SIG 1 , SIG 2 , SIG 3 and SIG 4 by twelve sets of output switches, two for each column, including switch sets SW 3 and SW 4 for the first column, switch sets SW 5 and SW 6 for the second column, and so on until the sixth column for which the output is controlled by switch sets SW 13 and SW 14 . Line signals SIG 1 and SIG 2 receive the outputs from the first, third and fifth columns, while line signals SIG 3 and SIG 4 receive the outputs from the second, fourth and sixth columns. The signals on line signals SIG 1 to SIG 4 are amplified by signal amplifiers 305 and become amplified line signals SIG 1 ′ to SIG 4 ′.

The goal of the circuit in FIGS. 5A and 5B is to simultaneously place on the pairs of line signals SIG 1 and SIG 2 , or SIG 3 and SIG 4 , signals from pixels from adjacent rows so that they can be further processed. For example, during a second time period (assuming the first time period was used to store a first set of values), the first and second pixels from the first column would be simultaneously read, then the first and second pixels from the second column would be simultaneously read, and so on until the sixth column where the first and second pixels from that column would be simultaneously read.

More specifically, with reference to FIGS. 5A and 5B, from the first column, pixel 103 A would be simultaneously read with pixel 103 B on line signals SIG 1 and SIG 2 , respectively, then from the second column, pixel 103 E would be simultaneously read with pixel 103 F on line signals SIG 3 and SIG 4 , respectively, then from the third column, pixel 103 I would be simultaneously read with pixel 103 J on line signals SIG 1 and SIG 2 , respectively, and so on until the sixth column where pixel 103 U would be simultaneously read with pixel 103 V on line signals SIG 3 and SIG 4 , respectively.

During the third time period, the second and third pixels from each column would be simultaneously read in a similar manner. Then, in the fourth time period, the third and fourth pixels from each column would be simultaneously read. These simultaneous readings of pixels from different rows are accomplished by the use of storage capacitors C 1 to C 24 which store the signal from each pixel on two capacitors during different time periods. Two capacitors are needed for each signal since each pixel signal (with the exception of the first and last pixel in each column) is read twice. For example, pixel 103 B is simultaneously read with pixel 103 A and then later with pixel 103 C.

The operation of the circuit of FIGS. 5A and 5B is illustrated by the timing diagrams shown in FIG. 6 . As shown in FIG. 6, an H-SYNC signal synchronizes the reading times of the processing circuitry. At the beginning of time period 1 , the pixel control signal P 1 goes high at the same time as switch set SW 1 . This causes the signals from the first row of pixels, including pixels 103 A, 103 E, 103 I, 103 M, 103 Q and 103 U, to be amplified by signal amplifiers 205 and be stored on capacitors in sets of two. Specifically, capacitors C 1 and C 2 store the pixel signal 103 A, capacitors C 5 and C 6 store the pixel signal 103 E, capacitors C 9 and C 10 store the pixel signal 103 I, and so on until capacitors C 21 and C 22 , which store the pixel signal 103 U. Thus, each of the pixel signals is stored on two capacitors, and these two stored pixel signals are referenced as stored pixel signals 103 A′ and 103 A″ for pixel 103 A, stored pixel signals 103 E′ and 103 E″ for pixel 103 E, and so on.

Next, output switches of odd number SW 3 , SW 5 , SW 7 , SW 9 , SW 11 and SW 13 are activated in consecutive sequential order, which causes the signals from the capacitors C 1 , C 5 , C 9 , C 13 , C 17 and C 21 to be alternately placed on line signals SIG 1 and SIG 3 . Thus, the pixels of a particular row are read sequentially. In this embodiment, the signals which are placed on line signal SIG 1 come from capacitors C 1 , C 9 and C 17 , which in turn come from pixels 103 A, 103 I and 103 Q, which are all color CLR 1 pixels. The signals on line signal SIG 3 come from capacitors C 5 , C 13 and C 21 , which come from pixels 103 E, 103 M and 103 U, which are all color CLR 3 pixels. Thus, line signal SIG 1 is receiving first row color CLR 1 signals and line signal SIG 3 is receiving first row color CLR 3 signals.

Although the timing diagrams show the names of the pixel signals (signal 103 A′ is abbreviated as A′, etc.) which are transferred to the line signals after the output switch sets SW 3 to SW 14 are activated, it is understood that the named signals do not necessarily remain on the line signals for the full time period shown in the diagram, and are shown there only for purposes of illustration as if the charge from each of the capacitors had been transferred to each of the line signals. Line signals SIG 1 and SIG 2 are obtained simultaneously, as are line signals SIG 3 and SIG 4 , although during time period 1 the output lines SIG 2 and SIG 4 have not been shown to be charged with any signals.

At the beginning of time period 2 , the pixel control signal P 2 goes high at the same time as switch set SW 2 . This causes the signals from the second row of pixels 103 B, 103 F, 103 J, 103 N, 103 R and 103 V (which include color CLR 2 and color CLR 4 pixels), to be amplified by signal amplifiers 205 , and be stored on capacitors in sets of two. Specifically, capacitors C 3 and C 4 store the pixel signal 103 B, capacitors C 7 and C 8 store the pixel signal 103 F, capacitors C 11 and C 12 store the pixel signal 103 J, and so on, until capacitors C 23 and C 24 , which store the pixel signal 103 V. Thus, each of the pixel signals is stored on two capacitors, and these two stored pixel signals are referenced as stored pixel signals 103 B′ and 103 B″, respectively, for pixel 103 B, stored pixel signals 103 F′ and 103 F″ for pixel 103 F, and so on. Next, output switches of even number SW 4 , SW 6 , SW 8 , SW 10 , SW 12 and SW 14 activate in consecutive order, which cause the signals from capacitors C 4 , C 8 , C 12 , C 16 , C 20 and C 24 to be alternately placed on line signals SIG 2 and SIG 4 , and also simultaneously cause the signals from capacitors C 2 , C 6 , C 10 , C 14 , C 18 and C 22 , which were stored during time period 1 , to be alternately placed on line signals SIG 1 and SIG 3 .

The signals which are placed on line signal SIG 1 came from capacitors C 2 , C 10 and C 18 , which were stored during time period 1 , which in turn came from first row pixels 103 A, 103 I and 103 Q, which are all color CLR 1 pixels. The signals on line signal SIG 2 came from capacitors C 4 , C 12 and C 20 , which were stored during time period 2 , which in turn came from second row pixels 103 B, 103 J and 103 R which are all color CLR 2 pixels. Thus, at the points in time period 2 when the switch sets SW 4 , SW 8 and SW 12 activate, the line signals SIG 1 and SIG 2 simultaneously contain signals from pixels 103 A and 103 B, then 103 I and 103 J, and then 103 Q and 103 R, respectively. These are all simultaneous readings of first row color CLR 1 pixels with adjacent second row color CLR 2 pixels, as is the goal of the system.

Similarly, the signals on line signal SIG 3 , which are being placed at alternating times from the simultaneous signals on output lines SIG 1 and SIG 2 , came from capacitors C 6 , C 14 and C 22 , which were stored during time period 1 , which in turn came from first-row pixels 103 E, 103 M and 103 U, which are all color CLR 3 pixels. The signals on line signal SIG 4 came from capacitors C 8 , C 16 and C 24 , which were stored during time period 2 , which in turn came from second-row pixels 103 F, 103 N and 103 V, which are all color CLR 4 pixels. Thus, at the points during time period 2 when switch sets SW 6 , SW 10 and SW 14 activate, line signals SIG 3 and SIG 4 simultaneously contain signals from pixels 103 E and 103 F, then 103 M and 103 N, and then 103 U and 103 V, respectively. These are all simultaneous readings of first row color CLR 3 pixels with adjacent second-row color CLR 4 pixels, as is the goal of the system. Thus, the complete output during time period 2 is simultaneous readings of first row color CLR 1 pixels with adjacent second row color CLR 2 pixels on line signals SIG 1 and SIG 2 , respectively, alternating with simultaneous readings of first row color CLR 3 pixels with adjacent second row color CLR 4 pixels on output lines SIG 3 and SIG 4 , respectively, in consecutive order of the pixels in FIG. 5A moving from left to right.

At the beginning of time period 3 , the pixel control signal P 3 goes high at the same time as switch set SW 1 . This causes the signals from the third row of pixels 103 C, 103 G, 103 K, 103 O, 103 S and 103 W (which include color CLR 1 and color CLR 3 pixels), to be amplified by signal amplifiers 205 , and be stored on capacitors in sets of two. Specifically, capacitors C 1 and C 2 store the pixel signal 103 C, capacitors C 5 and C 6 store the pixel signal 103 G, and so on until capacitors C 21 and C 22 which store the pixel signal 103 W. Thus, each of the pixel signals is stored on two capacitors, and for pixel 103 C these two stored pixel signals are referenced as stored pixel signals 103 C′ and 103 C″, respectively, and for pixel 103 G they are stored pixel signals 103 G′ and 103 G″, and so on. Next, output switches of odd number SW 3 , SW 5 , SW 7 , SW 9 , SW 11 and SW 13 , activate in consecutive order, which cause the signals from capacitors C 1 , C 5 , C 9 , C 13 , C 17 and C 21 to be alternately placed on line signals SIG 1 and SIG 3 , and also simultaneously cause the signals from capacitors C 3 , C 7 , C 11 , C 15 , C 19 and C 23 , which were stored during time period 2 , to be alternately placed on line signals SIG 2 and SIG 4 .

The signals which are placed on line signal SIG 1 came from capacitors C 1 , C 9 and C 17 , which were stored during time period 3 , which in turn came from third-row pixels 103 C, 103 K and 103 S, which are all color CLR 1 pixels. The signals on line signal SIG 2 came from capacitors C 3 , C 11 and C 19 , which were stored during time period 2 , which in turn came from second-row pixels 103 B, 103 J and 103 R which are all color CLR 2 pixels. Thus, at the points during time period 3 when switch sets SW 3 , SW 7 and SW 11 activate, the line signals SIG 1 and SIG 2 simultaneously contain signals from pixels 103 C and 103 B, then 103 K and 103 J, and then 103 S and 103 R, respectively. These are all simultaneous readings of third row color CLR 1 pixels with adjacent second row color CLR 2 pixels, as is the goal of the system.

Similarly, the signals on line signal SIG 3 , which are being placed at alternating times from the simultaneous signals on line signals SIG 1 and SIG 2 , came from capacitors C 5 , C 13 and C 21 , which were stored during time period 3 , which in turn came from third-row pixels 103 G, 1030 and 103 W, which are all color CLR 3 pixels. The signals on line signal SIG 4 came from capacitors C 7 , C 15 and C 23 , which were stored during time period 2 , which in turn came from second-row pixels 103 F, 103 N and 103 V, which are all color CLR 4 pixels. Thus, at the points during time period 3 when the switch sets SW 5 , SW 9 and SW 13 activate, the line signals SIG 3 and SIG 4 simultaneously compare signals from pixels 103 G and 103 F, then 1030 and 103 N, and then 103 W and 103 V, respectively. These are all simultaneous readings of third row color CLR 3 pixels with adjacent second-row color CLR 4 pixels, as is the goal of the system. Thus, the complete output during time period 3 is simultaneous readings of third row color CLR 1 pixels with adjacent second row color CLR 2 pixels on line signals SIG 1 and SIG 2 , alternating with simultaneous readings of third row color CLR 3 pixels with adjacent second row color CLR 4 pixels on line signals SIG 3 and SIG 4 , in consecutive order of the pixels in FIG. 5A moving from left to right.

During time period 4 (not shown), the process repeats as it did during time period 2 , so as to allow simultaneous readings of third row color CLR 1 pixels with adjacent fourth row color CLR 2 pixels on line signals SIG 1 and SIG 2 , alternating with simultaneous readings of third row color CLR 3 pixels with adjacent fourth row color CLR 4 pixels on line signals SIG 3 and SIG 4 , in consecutive order of the pixels in FIG. 5A moving from left to right.

FIGS. 7A and 7B illustrate an alternate embodiment of the present invention. FIG. 7A is identical to FIG. 5A, with the exception that a new fifth row of pixels has been added, as is needed for the timing descriptions of FIGS. 8A, 8 B, 11 A, and 11 B, as described below. The new fifth row of pixels has been designated as pixels 103 Y, 103 Z, 103 a, 103 b, 103 c and 103 d, running from left to right. As was described for FIGS. 5A and 5B above, FIG. 7B is coupled to a pixel array such as that shown in FIG. 7A, such that signal line SIG 1 ultimately carries color CLR 1 signals, signal line SIG 2 carries color CLR 2 signals, signal line SIG 3 carries color CLR 3 signals, and signal line SIG 4 carries color CLR 4 signals.

The circuitry of FIG. 7B may generally be referred to as an interlace reading structure. In general, an interlace reading structure performs separate even and odd field reading operations, as will be described in more detail below. FIG. 7B is similar to FIG. 5B, except that only two capacitors are associated with each column of the six column pixel array, rather than four capacitors, as was shown in FIG. 5 B. As was described previously with reference to FIG. 5B, signal amplifiers 205 may be charge amplifiers or voltage amplifiers, and the pixels may be active or passive, and there may also be sample buffers inserted after the capacitors. For purposes of illustration, the numbering scheme of the capacitors of FIG. 5B has been maintained, with the even numbered capacitors having been removed. Thus, the first column has capacitors C 1 and C 3 associated with it, the second column has capacitors C 5 and C 7 associated with it, and so on until the sixth column, which has the capacitors C 21 and C 23 associated with it. As a result, only the odd numbered switches SW 3 , SW 5 , SW 7 , SW 9 , SW 11 , and SW 13 , which are coupled to the odd numbered capacitors, are needed for switching the signals from the capacitors. As was described for FIG. 5B, signal lines SIG 1 and SIG 2 receive the outputs from the first, third, and fifth columns, while signal lines SIG 3 and SIG 4 receive the outputs from the second, fourth, and sixth columns.

The operation of the reading structure of FIGS. 7A and 7B is illustrated by the timing diagrams shown in FIGS. 8A, 8 B and 9 . FIGS. 8A and 8B are somewhat similar to FIG. 6, except that FIG. 8A shows timing diagrams for an even field reading operation and FIG. 8B shows timing diagrams for an odd field reading operation. FIG. 9 shows the overall timing diagrams for both FIGS. 8A and 8B for one frame of TV timing.

As shown in FIG. 8A, an H-SYNC signal synchronizes the reading times of the processing circuitry. At the beginning of time period 1 , the pixel control signal P 1 goes high at the same time as switch set SW 1 . This causes the signals from the first row of pixels, including pixels 103 A, 103 E, 103 I, 103 M, 103 Q and 103 U, to be amplified by signal amplifiers 205 and be stored on the capacitors C 1 , C 5 , C 9 , C 13 , C 17 and C 21 , respectively. Next, the pixel control signal P 2 goes high at the same time as switch set SW 2 . This causes the signals from the second row of pixels, including pixels 103 B, 103 F, 103 J, 103 N, 103 R, and 103 V to be amplified by signal amplifiers 205 and be stored on capacitors C 3 , C 7 , C 11 , C 15 , C 19 , and C 23 , respectively. Next, the output switches SW 3 , SW 5 , SW 7 , SW 9 , SW 11 , and SW 13 are activated in consecutive order, which causes the signals from adjacent pixels that were stored on the capacitors to be simultaneously placed on pairs of the signal lines SIG 1 and SIG 2 , or SIG 3 and SIG 4 . It will be noted that signal line SIG 1 receives all of the color CLR 1 pixel signals (from pixels 103 A, 103 I and 103 Q), while signal line SIG 2 receives all of the color CLR 2 pixel signals (from pixels 103 B, 103 J, and 103 R). Also, signal line SIG 3 receives all of the color CLR 3 pixel signals (from pixels 103 E, 103 M, and 103 U), while signal line SIG 4 receives all of the color CLR 4 pixel signals (from pixels 103 F, 103 N, and 103 V). In this manner, during time period 1 , the entire first row of pixels is read out onto signal lines SIG 1 , and SIG 3 , while the entire second row of pixels is read out onto signal lines SIG 2 and SIG 4 . This accomplishes the goal of the system by simultaneously reading out first row pixels with adjacent second row pixels, similar to as was described for FIG. 6, above, during time period 2 .

As illustrated in FIG. 8A, during time period 2 , the process that occurred during time period 1 repeats, except that during time period 2 , pixel control signal P 3 goes high at the same time as switch set SW 1 , and thereafter pixel control signal P 4 goes high at the same time as switch set SW 2 . This causes the pixel signals from the third and fourth rows of pixels to be stored on the capacitors in the same manner as the first and second rows during time period 1 . Switches SW 3 , SW 5 , SW 7 , SW 9 , SW 11 , and SW 13 are then again activated in consecutive order, which causes the signals from adjacent pixels in rows three and four to be simultaneously read out onto pairs of signal lines SIG 1 and SIG 2 , or SIG 3 and SIG 4 .

The timing diagrams of FIG. 8B for the odd field reading operation are similar to those of FIG. 8A for the even field reading operation, with the exception that the pixel control signals are operated in a different order. During time period 1 of FIG. 8B, the pixel control signal P 3 goes high at the same time as switch set SW 1 , and thereafter pixel control signal P 2 goes high at the same time as switch set SW 2 . Switches SW 3 , SW 5 , SW 7 , SW 9 , SW 11 , and SW 13 are then activated in consecutive order. This causes the pixel signals from adjacent pixels in the third and second rows of the pixel array to be read out simultaneously on pairs of signal lines SIG 1 and SIG 2 , or SIG 3 and SIG 4 .

The process repeats in time period 2 of FIG. 8B, except that pixel control signal P 5 goes high at the same time as switch set SW 1 , after which pixel control signal P 4 goes high at the same time as switch set SW 2 . Switches SW 3 , SW 5 , SW 7 , SW 9 , SW 11 , and SW 13 are then activated in consecutive order. This causes pixel signals from adjacent pixels in rows five and four of the pixel array to be simultaneously read out on pairs of signal lines SIG 1 and SIG 2 or SIG 3 and SIG 4 .

FIG. 9 illustrates the overall timing operations for FIGS. 8A and 8B as coordinated for one frame of TV timing. In the example of FIG. 9, there are assumed to be approximately 480 rows of pixels in the pixel array that is being read out, thus requiring approximately 240 periods in each of the even and odd fields. As illustrated, a control signal V-SYNC first coordinates the reading out of the even field, and then coordinates the reading out of the odd field. The even field and the odd field combine to form one frame of TV timing.

As described above, the reading operation for the timing diagrams of FIGS. 8A and 8B for the interlace structure differs from that of the timing diagrams for FIG. 6 for a non-interlace structure, in that in FIGS. 8A and 8B, each pixel signal only needs to be stored once, whereas in FIG. 6, each pixel signal needs to be stored twice. This is because in FIG. 6, for a non-interlace structure each pixel is compared first to the adjacent pixel in the row before it, and then in the next timing period is compared to the adjacent pixel in the row after it. Thus, row 1 is first compared to row 2 , then row 2 is compared to row 3 , then row 3 is compared to row 4 , and so on. In contrast, in FIGS. 8A and 8B, for an interlace reading structure each pixel is only compared to an adjacent pixel for a given even or odd field reading. Thus, in the even field, row 1 is compared to row 2 , then row 3 is compared to row 4 , then row 5 is compared to row 6 , and so on, while for the odd field, row 2 is compared to row 3 , then row 4 is compared to row 5 , and so on. Thus, in both non-interlace and interlace reading structures, each pixel signal is stored twice, although in the non-interlace structure it is stored twice at the same time, while in the interlace structure it is stored once during the even field and once during the odd field. As a result, the circuitry of FIG. 7B only requires half as many storage capacitors as are required for FIG. 5 B.

Another embodiment of the present invention is illustrated in FIG. 10 . FIG. 10 illustrates an interlace circuit that is somewhat similar to FIG. 7B, in that only half the number of capacitors of FIG. 5B are required. FIG. 10 differs from FIG. 7B in that only two reading channel signal lines, SIG 1 and SIG 2 , are used rather than the four reading channel signal lines SIG 1 -SIG 4 that were used in FIG. 7 B. Thus, in FIG. 10, all of the switches SW 3 , SW 5 , SW 7 , SW 9 , SW 11 , and SW 13 are coupled only to signal lines SIG 1 and SIG 2 . As a result, the signals from all of the pixels 103 are placed on either signal line SIG 1 or signal line SIG 2 .

FIGS. 11A and 11B illustrate the even and odd field timing diagrams for the circuit of FIG. 10 . The timing for the H-SYNC, pixel control signals P 1 -P 4 , and switches SW 1 , SW 2 , SW 3 , SW 5 , SW 7 , SW 9 , SW 11 , and SW 13 are identical to those for the even and odd fields of FIGS. 8A and 8B.

As illustrated in FIG. 11A, during time period 1 , the pixel signals from the entire first row of pixels (from pixels 103 A, 103 E, 103 I, 103 M, 103 Q, and 103 U) are read out onto signal line SIG 1 , and the signals from the entire second row of adjacent pixels (from pixels 103 B, 103 F, 103 J, 103 N, 103 R, and 103 V) are simultaneously read out onto signal line SIG 2 . During time period 2 , adjacent pixels from the third and fourth rows of pixels are simultaneously read out onto the pair of signal lines SIG 1 and SIG 2 . FIG. 11B repeats this process, except for reading out the third and second rows of pixels during time period 1 , and the fifth and fourth rows of pixels during time period 2 .

Thus, FIGS. 5B, 7 B, and 10 all illustrate various embodiments of the invention that allow two or more rows of pixels to be simultaneously read out, using technology such as capacitors or other storage cells that are external to the pixels but are also easily fabricated on a MOS chip. The circuitry of FIG. 7A with four reading channels has several advantages over the circuitry of FIG. 10 which has only two reading channels. As described above, with four reading channels each of the four colors of the pixel array may be directed to a separate reading channel. This structure allows the color processing circuits to be dramatically simplified over the two reading channel structure. In the two channel reading structure, each channel reads two colors, which must then be separated before performing color processing.

Another advantage of the circuitry of FIG. 7B over that of FIG. 10 is that the speed requirement is cut in half. This is because with four channels instead of two, each pixel signal can stay on a respective channel for twice as long, and achieve the same overall readout rate. For example, as can be seen for signal line SIG 1 during time period 1 in FIG. 8A, the signal from pixel 103 A is placed on signal line SIG 1 when switch SW 3 goes high, but is not removed until switch SW 7 goes high. In contrast, as shown in FIG. 11A during time period 1 , the signal from pixel 103 A is placed on signal line SIG 1 when switch SW 3 goes high and is removed when switch SW 5 goes high. Thus, the pixel signal from pixel 103 A is able to remain on signal line SIG 1 twice as long in FIG. 8A as it is in FIG. 11 A.

While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention. For example, in the reading structure of FIG. 5B, by altering the timing and placement of the switches SW 3 to SW 14 , signal lines SIG 1 to SIG 4 could even be for combinations of colors from more than one pixels, such as SIG 1 being for Cy+G, SIG 2 being for Ye+Mg, SIG 3 being for Cy+Mg and SIG 4 being for Ye+G, where Cy is cyan, G is green, Ye is yellow and Mg is magenta, as is used in many CCD color image sensors.

As another example, the description herein has been made in terms of reading adjacent rows of a pixel array. However, it can be appreciated that adjacent columns may be read just as easily, the distinction between a row and a column being merely semantic for a pixel array. Also, although the storage devices used to store the pixel signals are capacitors, it can be appreciated that any circuit element that has memory ability may be used, such as DRAMs, SRAMs, EEPROMS, and the like. Also, the structure described herein can easily be applied to more lines than are shown. While color TV processing usually uses two-line structures, other applications may use many more. Thus, the invention should not be limited to the preferred embodiment described herein, but should be limited only by the claims below.