Constant impedance for switchable amplifier with power control

1. Field of the Invention

The present invention relates to radio frequency (RF) power amplifiers.

2. State of the Art

In many RF communications systems, particularly cellular telephone systems, an RF transmitter portion of an RF transceiver is operated intermittently. In the GSM cellular telephone system, for example, communications are structured on a TDMA (Time Division Multiple Access) basis in which a communications frame comprises some number of timeslots, e.g., eight or sixteen. A particular handset transmits only within its assigned timeslot(s). During the remaining timeslots, the handset does not transmit, meaning that its RF power amplifier is turned off. Hence, the RF power amplifier is repeatedly turned on to transmit during its timeslot and then turned off.

The RF power amplifier is the major consumer of power within a radio transceiver. Unless proper precautions are taken, turning the power amplifier on can create an inrush condition that disturbs other transceiver circuitry. In particular, a PLL (phase lock loop) of the transceiver is susceptible to “frequency pulling” in which turning on the power amplifier disturbs the PLL lock condition. Frequency pulling is not only undesirable but in certain communication systems, such as GSM, is intolerable.

The same problem arises to a lesser degree in connection with power level adjustments. As the distance between a mobile handset and a fixed base station varies, the handset may be commanded to adjust its transmission power upward or downward. Such power control actions may also cause frequency pulling.

Various solutions to the problem of frequency pulling have been proposed.

U.S. Pat. No. 5,424,692 to McDonald, for example, incorporated herein by reference, describes a switchable impedance circuit used at both the input port and the output port of a RF power amplifier. The switchable impedance circuit receives a power down control signal. When the power down control signal is asserted, the switchable impedance circuits switch into alternate impedance states, whereby the “powered down” input impedances at the input and output ports, respectively, appear substantially unchanged in relation to the corresponding “powered up” impedances. In essence, the reference teaches the use of switches in series and shunt along the signal transmission line to selectively connect a through-path or a shunt path.

U.S. Pat. No. 5,774,017 to Adar, incorporated herein by reference, describes an amplifier, operable in two predetermined frequency bands, wherein the input impedance is controlled by using switches to select passive elements in series with the input transmission line. The reference also teaches using shunt switching elements to change interstage matching frequency responses. Since no mention is made of how output power is to be controlled, it appears that the amplifier must operate linearly, with output power being varied by changing the input power applied to the amplifier(s).

There remains a need for an improved power amplifier that further minimizes impedance changes as the power amplifier changes from one operational state to another.

The present invention, generally speaking, provides an improved power amplifier that minimizes impedance changes as the power amplifier changes from one operational state to another. In an exemplary embodiment, the present power amplifier is based on the well-known cascode amplifier. In a cascode amplifier, a first transistor operates in the common-source (common emitter) configuration to convert the input signal voltage (or current) into an amplified current, and a second transistor operates in the common-gate (common-base) configuration to convert the output current from the first transistor into an output voltage.

Unlike the prior art, the present power amplifier uses no selectable passive elements to set or adjust the input impedance. There are no separate transistors performing series and/or shunt switching functions. Rather, all transistors are integral parts of the actual signal amplifiers. Multiple second cascode transistors may be provided, connected to a single first cascode transistor. By controlling the bias voltage at the common element of these second cascode transistors, one or more of them may be selected to operate on the current supplied by the first cascode transistor.

The input impedance presented by the first cascode transistor is dependent on its bias conditions. With the bias conditions set, the input impedance of the total cascode amplifier remains effectively constant, irrespective of the second cascode transistor(s) that is (are) operating.

The bias of the second cascode transistors may be set so that multiple transistors can operate simultaneously. If only one second cascode transistor is ultimately desired to operate at any particular time, then the control bias can be smoothly transferred from one transistor to the other. Such selectivity is accomplished without the conventional, “snapping” switch action. Sudden transients that are usually not desirable in radio circuitry are thereby avoided.

With the provision for a potentially unlimited number of second cascode transistors, multi-mode and multi-band amplifiers can be constructed. Possibilities include: improving input-to-output isolation by using one load that is connected to no following circuitry; having load networks on separate second cascode transistors tuned to separate frequencies; and so on.

The present invention may be further understood from the following description in conjunction with the appended drawing. In the drawing:

FIG. 1 is a circuit diagram of a controlled impedance input circuit in accordance with an exemplary embodiment of the invention;

FIG. 2 is a circuit diagram showing a variation of the circuit of FIG. 1;

FIG. 3 is a circuit diagram showing a multi-band amplifier circuit; and

FIG. 4 is a circuit diagram showing another embodiment of the invention.

The present invention is particularly applicable to the use of high efficiency amplifiers, which operate in a highly nonlinear manner. Such nonlinear amplifiers can be controlled to provide a widely varying amount of output power while the input signal is maintained as disclosed in U.S. patent application Ser. No. 09/247,097 of the present assignee, entitled HIGH EFFICIENCY AMPLIFIER OUTPUT LEVEL AND BURST CONTROL filed on Feb. 9, 1999 and incorporated herein by reference. It is very important that the input impedance of such a power controlled amplifier be maintained constant while the output power varies, so that transients are not excited in the driving circuitry. In the preferred embodiment of the present invention, input impedance is maintained constant within 0.5% over the variation of output power of 95 dB.

Referring now to FIG. 1, a circuit diagram is shown of a power amplifier in accordance with an exemplary embodiment of the invention. A differential transistor pair is provided consisting of transistors T L and T R . In the illustrated embodiment, the transistors are FETs. In other embodiments, the transistors could be of other types, including bipolar transistors. The source electrodes of the transistors T L and T R are connected together, forming the “tail” of the differential pair. The drain electrodes are connected through respective loads Load L and Load R to an operating potential.

A third transistor, tail transistor T T , is connected with its drain electrode coupled to source electrodes of the transistors T L and T R and its source electrode coupled to a reference voltage.

Thus far, the description of the power amplifier applies equally well to a conventional differential pair. However, the present power amplifier differs dramatically from a conventional differential pair is several respects, to be presently described. In a conventional differential pair, a differential input signal is applied to the control terminals (e.g., gate electrodes) of the differential pair. A fixed bias is applied to the tail transistor, causing a fixed tail current to flow through the differential pair.

In the present power amplifier, by contrast, a control signal, V CTL , is applied to the gate electrode of the transistor T L . The gate electrode of the transistor T R is grounded. Alternatively, the inverse control signal, {overscore (V)} {overscore (CTL)} , may be applied to the gate electrode of the transistor T R as described hereinafter. A quiescent operating point of the tail transistor T T is set by a bias network including a resistor R and a source of bias potential, V bias . The gate of the tail transistor T T is coupled through the resistor R to the voltage V bias . Also applied to the gate of the tail transistor T T is the input signal RF in , which is capacitively coupled through a capacitor C. The output of the circuit is taken at the drain of the transistor T R , which is coupled to one or more amplifier stages.

The transistors T T and T R form a cascode amplifier, an amplifier stage composed of (in the case of FETs) a direct-coupled common-source/common-gate combination. The cascode amplifier exhibits very wide bandwidth. In addition, the transistor T R provides very good isolation between the input and output circuits, effectively eliminating capacitive feedback effects.

In operation, assume that the control signal V CTL is low such that the transistor T L is turned off. Then only the transistors T T and T R belonging to the cascode amplifier are active. In this configuration, the input impedance Z in depends on the voltage across the drain and source (or, in the case of bipolar transistors, collector and emitter) nodes of the transistor T T , and on the current flowing through these nodes. By using the cascode structure in this way, the voltage across the drain and source nodes is maintained effectively constant. The bias circuitry sets the current through these nodes of the first cascode transistor. Thus the input impedance of the total cascode amplifier remains effectively constant.

Now, as the control signal V CTL is raised, the transistor T L will begin to conduct and, if raised to a sufficient positive level, will conduct more than the transistor T R until the transistor T R eventually turns off. A differential action occurs, but with respect to the control signal V CTL , not the RF signal itself. The differential action is used to control through which leg of the differential stage the tail current flows and hence which of the associated cascode RF stages are powered up and which are powered down.

If the gate of the transistor T R is grounded, then the input impedance Z in will vary slightly depending on the state of the control signal V CTL . Alternatively, the inverse control signal, {overscore (V)} {overscore (CTL)} , may be applied to the gate electrode of the transistor T R as illustrated in FIG. 2 . In this arrangement, variations in the input impedance are negligible.

Multiple second cascode transistors may be provided, connected to a single first cascode transistor. By controlling the bias voltage at the common element of these second cascode transistors, one or more of them may be selected to operate on the current supplied by the first cascode transistor.

The input impedance presented by the first cascode transistor is dependent on its bias conditions. With the bias conditions set, the input impedance of the total cascode amplifier remains effectively constant, irrespective of the second cascode transistor(s) that is (are) operating.

The bias of the second cascode transistors may be set so that multiple transistors can operate simultaneously. If only one second cascode transistor is ultimately desired to operate at any particular time, then the control bias can be smoothly transferred from one transistor to the other. Such selectivity is accomplished without the conventional, “snapping” switch action. Sudden transients that are usually not desirable in radio circuitry are thereby avoided.

With the provision for a potentially unlimited number of second cascode transistors, multi-mode and multi-band amplifiers can be constructed. Possibilities include: improving input-to-output isolation by using one load that is connected to no following circuitry; having load networks on separate second cascode transistors tuned to separate frequencies; and so on. Different ones of these possibilities are illustrated in FIG. 3 and FIG. 4, respectively.

Referring to FIG. 3, an amplifier circuit having two legs is provided. Within each leg, a power amplifier is connected to receive as an input voltage the voltage developed across the load. The power amplifiers of the two legs are optimized for different frequency bands, Band 1 and Band 2 , respectively.

Referring to FIG. 4, an amplifier circuit having more than two legs is provided. Multiple bands are provided for in like manner as in FIG. 3 . In addition, a load of one of the legs of the differential amplifier circuit serves as a dummy load; i.e., one load is connected to no following circuitry. When this leg of the differential amplifier circuit is selected, there results an isolation mode in which the RF input is isolated from downstream amplifying circuitry that produces the final RF output.

In other embodiments, the RF stages associated with different legs of the differential amplifier may be coupled to different antennas, providing transmit diversity. The present controlled impedance input circuit provides a convenient and efficient way to switch between antennas, by switching at the early stages of amplification instead of switching a high-power signal.

It will be appreciated by those of ordinary skill in the art that the invention can be embodied in other specific forms without departing from the spirit or essential character thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than the foregoing description, and all changes which come within the meaning and range of equivalents thereof are intended to be embraced therein.