Semiconductor device and manufacturing method thereof

A semiconductor device having a power transistor structure comprising: a semiconductor layer of a first conductivity type; a first well of a second conductivity type disposed on said semiconductor layer; a second well of the first conductivity type disposed at a surface region of said first well; a drain region disposed within said second well; a channel well region of the second conductivity type disposed at the surface region to be connected to said first well; a source region of the first conductivity type disposed within said channel well region; a gate electrode disposed over a surface portion of said channel well region between said source region and said second well where said drain region is disposed, thereby said second well serving as a drift region; and an electrode electrically connected to said semiconductor layer to maintain a potential on said semiconductor layer, wherein a parasitic bipolar transistor structure collectively formed by said second well, said first well and said semiconductor layer is designed to create a vertical current-carrying path from said second well through said first well and said semiconductor layer is designed to create a vertical current-carrying path from said second well through said first well to said semiconductor layer when an excessive voltage is applied to said drain region, and wherein said source region and said semiconductor layer are set to be electrically equipotential via said electrode.

A semiconductor device comprising: a supporting semiconductor substrate; an insulation film disposed on said supporting semiconductor substrate; a buried semiconductor layer of a first conductivity type disposed on said supporting semiconductor substrate with said insulation film interposed therebetween; a first well of a second semiconductor type disposed on said buried semiconductor layer; a second well of the first conductivity type disposed at a surface region of said first well; a drain region disposed within said second well; a channel well region of the second conductivity type disposed at the surface region to be connected to said first well; a source region of the first conductivity type disposed within said channel well region; a gate electrode disposed over a surface portion of said channel well region between said source region and said second well where said drain region is disposed, thereby said second well serving as a drift region; a electrode electrically connected to said buried semiconductor layer to maintain a fixed potential on said buried semiconductor layer; and a base region of the second conductivity type disposed to overlap with a region of said channel well region beneath said source region and contact down to said first well.

A semiconductor device having a power transistor structure comprising: a semiconductor layer of a first conductivity type; a first well of a second conductivity type disposed on said semiconductor layer; a second well of the first conductivity type disposed at a surface region of said first well; a drain region disposed within said second well; a channel well region of the second conductivity type disposed at the surface region to be connected to said first well; a source region of the first conductivity type disposed within said channel well region; a gate electrode disposed over a surface portion of said channel well region between said source region and said second well where said drain region is disposed, thereby said second well serving as a drift region; an electrode electrically connected to said semiconductor layer to maintain a potential on said semiconductor layer, wherein a parasitic bipolar transistor structure collectively formed by said second well, said first well and said semiconductor layer is designed to create a vertical current-carrying path from second well through said first well to said semiconductor layer when an excessive voltage is applied to said drain region; and a base region of the second conductivity type disposed to overlap with a portion of said channel well region beneath said source region and contact down to said first well.