Analog to digital converter, encoder, and recorded data reproducing apparatus

An encoder comprising: a plurality of ROM cells, connected between a plurality of bit lines and a plurality of word lines, each of said ROM cells being responsive to a word line select signal supplied to a word line associated with each of said ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of said ROM cells; and at least one logic processor, coupled to one of said bit lines and to at least two of said word lines being used to select a ROM cell connected to said bit line, for producing an output signal indicative of a selection of said ROM cell connected to said bit line, based on word line select signals supplied on said at least two of said word lines.

An encoder for outputting digital output signals consisting of a plurality of bits in response to a plurality of word line select signals, said encoder comprising: a plurality of word lines; a plurality of bit lines, at least two of said bit lines being assigned to a specific one of said digital output signals selected from said plurality of bits, remaining ones of said bit lines being assigned to each of the remaining digital output signals; a plurality of ROM cells located between said plurality of bit lines and said plurality of word lines, each of said ROM cells being responsive to a word line select signal supplied to the word line associated with said ROM cell for supplying a digital output signal; and a logic circuit, connected to said at least two of said, bit lines, for obtaining an exclusive OR of digital signals on said at least two of said bit lines and for outputting therefrom the resultant signal as the specific one of said digital output signals.

An A/D converter comprising: a plurality of comparators for receiving an analog input voltage and a plurality of reference voltages respectively, said plurality of comparators being adapted to produce a group of outputs according to a thermometer code while each comparator compares said analog input voltage with one of said reference voltages applied to each of said comparators; a plurality of address decoders, coupled to said plurality of comparators, for producing address signals for selecting a specific address in response to the outputs of said comparators; and an encoder section, coupled to said address decoders, for producing digital output signals in response to said address signals, wherein said encoder section includes: a plurality of ROM cells, located between a plurality of bit lines and a plurality of word lines, each of said ROM cells being responsive to one of said address signals as a word line select signal supplied to the one word line associated with each of said ROM cells for supplying a digital output signal according to the word line select signal onto a bit line associated with each of said ROM cells; and at least one OR circuit, connected to a specific one of said bit lines and to at least two word lines used to select a ROM cell connected to said specific one of said bit lines, for producing an output signal indicative of a selection of said ROM cell connected to said specific one of said bit lines, based on the word line select signals supplied to said at least two word lines connected to said OR circuit.

An A/D converter comprising: a reference voltage generating circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input signal and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation in which each comparator compares one of said reference voltages applied thereto with said analog input signal, said plurality of comparators being adapted to produce a group of thermometer-code based output signals smaller by at least one in number than said comparators; an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; a control circuit coupled to said plurality of comparators, for controlling said plurality of comparators in such a way as to permit at least one of said comparators to perform a reset operation and to permit the remaining comparators to perform comparison operations; a first selecting circuit controllable by said control circuit and provided between said plurality of comparators and said encoder, for selectively supplying said encoder with the output signals of the comparators which are performing comparison operations as said group of thermometer-code based output signals; and a second selecting circuit controllable by said control circuit and provided between said reference voltage generating circuit and said plurality of comparators, for selectively distributing said plurality of analog reference voltages, produced by said reference voltage generating circuit, to said one of comparators associated with the reset operation and the remaining comparators associated with the comparison operations.

A semiconductor integrated circuit device comprising: an amplifier for amplifying a read signal externally supplied as an analog signal; a filter for eliminating high-frequency signal components from an output signal of said amplifier; an A/D converter for converting an analog output signal of said filter to a digital signal, said A/D converter including a reference voltage generating circuit for producing a plurality of different analog reference voltages, a plurality of comparators supplied with an analog input signal and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation in which each comparator compares one of said reference voltages applied thereto with said analog input signal, said plurality of comparators being adapted to produce a group of thermometer-code based output signals smaller by at least one in number than said comparators, an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators, a control circuit coupled to said plurality of comparators, for controlling said plurality of comparators in such a way as to permit at least one of said comparators to perform a reset operation and to permit the remaining comparators to perform comparison operations, a first selecting circuit controllable by said control circuit and provided between said plurality of comparators and said encoder, for selectively supplying said encoder with the output signals of the comparators which are performing comparison operations as said group of thermometer-code based output signals, and a second selecting circuit controllable by said control circuit and provided between said reference voltage generating circuit and said plurality of comparators, for selectively distributing said plurality of analog reference voltages, produced by said reference voltage generating circuit, to said one of comparators associated with the reset operation and the remaining comparators associated with the comparison operations; and an equalizer, supplied with said digital signal output from said A/D converter, for adapting said digital signal to a circuit at subsequent stage.

A semiconductor integrated circuit comprising: a prestage circuit for producing an analog signal; an A/D converter for converting said analog signal supplied from said prestage circuit to a first digital signal; an offset voltage canceling circuit for producing and outputting therefrom a second digital signal, said second digital signal for reducing an offset voltage supplied to said A/D converter from said prestage circuit, said second digital signal based on the first digital signal output from said A/D converter, when the supply of said analog signal to said AND converter from said prestage circuit is inhibited; and a D/A converter, connected to said prestage circuit and said offset voltage canceling circuit, for converting the second digital signal output from said offset voltage canceling circuit to an analog signal, wherein an offset voltage is canceled by said analog signal supplied to said prestage circuit from said D/A converter.

A recorded data reproducing apparatus comprising: a data reading device for reading data from a recording medium having a plurality of sectors, each sector having a servo area and a data area, and for outputting an analog data signal indicative of said read data; an A/D converting unit for converting said analog data signal to a first digital signal; and a digital signal processing unit for subjecting said first digital signal output from said A/D converting unit to digital processing, wherein said A/D converting unit includes: a switch circuit for inhibiting the analog data signal to be input to said A/D converting unit in response to a control signal output from said data reading device, when said data reading device accesses the servo area in each of said plurality of sectors; a prestage circuit for receiving said analog data signal from said data reading device via said switch circuit and for outputting the received analog data signal; an A/D converter for converting the analog data signal from said prestage circuit to said first digital signal; an offset voltage canceling circuit for producing and outputting therefrom a second digital signal to reduce an offset voltage supplied to said A/D converter from said prestage circuit, said second digital signal based on the first digital signal output from said A/D converter, when the supply of said analog signal to said A/D converter from said prestage circuit is inhibited; and a D/A converter, connected to said prestage circuit and said offset voltage canceling circuit, for converting the second digital signal output by said offset voltage canceling circuit to an analog signal, wherein the offset voltage is canceled by said analog signal supplied to said prestage circuit from said D/A converter.

An analog to digital converting method comprising the steps of: using a plurality of comparators, which receive a plurality of analog input signals and a plurality of different analog reference voltages; causing at least one of said comparators to perform a reset operation, and causing the remaining comparators to perform comparison operations; causing each of said remaining comparators to compare an analog input signal with an analog reference voltage, therein producing an output as the compared result; and producing plural bits of digital output signals based on the outputs from said remaining comparators performing comparison operations.

An A/D converter comprising: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation performed between the analog input voltage and an associated analog reference voltage, each comparator performing a plurality of comparison operations after performing the reset operation to output an output signal; and an encoder for producing a digital signal consisting of a plurality of bits based on tho output signals of said plurality of comparators.

An A/D converter comprising: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, said plurality of comparators including a first comparator performing a reset operation and a second comparator performing a comparison operation between an analog input voltage and an associated analog reference voltage to output an output signal, said first and second comparators operating in parallel in one converting cycle; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators.

An A/D converter comprising: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, each comparator performing a reset operation and a comparison operation between the analog input voltage and an associated analog reference voltage to output an output signal, said a plurality of comparators alternately performing said reset operation; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators.

An A/D converter comprising: a reference voltage generating circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input signal and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation in which each comparator compares one of said reference voltages applied thereto with said analog input signal; an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; a control circuit coupled to said plurality of comparators for controlling said plurality of comparators so as to permit at least one of said comparators to perform the reset operation and to permit the remaining comparators to perform the comparison operation; a first selecting circuit controllable by said control circuit and provided between said plurality of comparators and said encoder for selectively supplying said encoder with the output signals of the comparators that are performing the comparison operation; and a second selecting circuit controllable by said control circuit and provided between said reference voltage generating circuit and said plurality of comparators for selectively distributing said plurality of analog reference voltages to said comparators.

An A/D converter comprising: a reference voltage generating circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input signal and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation in which each comparator compares one of said reference voltages applied thereto with said analog input signal, said plurality of comparators being adapted to produce a group of thermometer-code based output signals smaller by at least one in number than said comparators; an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators, wherein said encoder includes: a plurality of ROM cells, connected between a plurality of bit lines and a plurality of word lines, each of said ROM cells being responsive to a word line select signal supplied to a word line associated with each of said ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of said ROM cells; and at least one logic processor, coupled to one of said bit lines and to at least two of said word lines being used to select a ROM cell connected to said bit line, for producing an output signal indicative of a selection of said ROM cell connected to said bit line, based on word line select signals supplied on said at least two of said word lines; a control circuit coupled to said plurality of comparators for controlling said plurality of comparators in such a way as to permit at least one of said comparators to perform the reset operation and to permit the remaining comparators to perform the comparison operation; a first selecting circuit controllable by said control circuit and provided between said plurality of comparators and said encoder for selectively supplying said encoder with the output signals of the comparators that are performing the comparison operation as said group of thermometer-code based output signals; and a second selecting circuit controllable by said control circuit and provided between said reference voltage generating circuit and said plurality of comparators, for selectively distributing said plurality of analog reference voltages to said comparators.

An A/D converter comprising: a reference voltage generating circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input signal and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation in which each comparator compares one of said reference voltages applied thereto with said analog input signal, said plurality of comparators being adapted to produce a group of thermometer-code based output signals smaller by at least one in number than said comparators; an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators, wherein said encoder includes: a plurality of word lines; a plurality of bit lines, at least two of said bit lines being assigned to a specific one of said digital output signals selected from said plurality of bits, a single one of said bit lines being assigned to each of the remaining digital output signals; a plurality of ROM cells located between said plurality of bit lines and said plurality of word lines, each of said ROM cells being responsive to a word line select signal supplied to the word line associated with said ROM cell for supplying a digital output signal; and a logic circuit, connected to said at least two of said bit lines, for obtaining an exclusive OR of digital signals on said at least two of said bit lines and for outputting therefrom the resultant signal as the specific one of said digital output signals; a control circuit coupled to said plurality of comparators for controlling said plurality of comparators in such a way as to permit at least one of said comparators to perform the reset operation and to permit the remaining comparators to perform the comparison operation; a first selecting circuit controllable by said control circuit and provided between said plurality of comparators and said encoder for selectively supplying said encoder with the output signals of the comparators that are performing the comparison operation as said group of thermometer-code based output signals; and a second selecting circuit controllable by said control circuit and provided between said reference voltage generating circuit and said plurality of comparators, for selectively distributing said plurality of analog reference voltages to said comparators.

An A/D converter comprising: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation performed between the analog input voltage and an associated analog reference voltage, each comparator performing a plurality of comparison operations after performing the reset operation to output an output signal; and an encoder for producing a digital signal consisting of a plurality of bits based of the output signals of said plurality of comparators, wherein said encoder includes: a plurality of ROM cells, connected between a plurality of bit lines and a plurality of word lines, each of said ROM cells being responsive to a word line select signal supplied to a word line associated with each of said ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of said ROM cells; and at least one logic processor, coupled to one of said bit lines and to at least two of said word lines being used to select a ROM cell connected to said bit line, for producing an output signal indicative of a selection of said ROM cell connected to said bit line, based on word line select signals supplied on said at least two of said word lines.

An A/D converter comprising: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation performed between the analog input voltage and an associated analog reference voltage, each comparator performing a plurality of comparison operations after performing the reset operation to output an output signal; and an encoder for producing a digital signal consisting of a plurality or bits based on the output signals of said plurality of comparators, wherein said encoder includes: a plurality of word lines; a plurality of bit lines, at least two of said bit lines being assigned to a specific one of said digital output signals selected from said plurality of bits, a single one of said bit lines being assigned to each of the remaining digital output signals; a plurality of ROM cells located between said plurality of bit lines and said plurality of word lines, each of said ROM cells being responsive to a word line select signal supplied to the word line associated with said ROM cell for supplying a digital output signal; and a logic circuit, connected to said at least two of said bit lines, for obtaining an exclusive OR of digital signals on said at least two of said bit lines and for outputting therefrom the resultant signal as the specific one of said digital output signals.

An A/D converter comprising: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, said plurality of comparators including a first comparator performing a reset operation and a second comparator performing a comparison operation between an analog input voltage and an associated analog reference voltage to output an output signal, said first and second comparators operating in parallel in one converting cycle; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators, wherein said encoder includes: a plurality of ROM cells, connected between a plurality of bit lines and a plurality of word lines, each of said ROM cells being responsive to a word line select signal supplied to a word line associated with each of said ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of said ROM cells; and at least one logic processor, coupled to one of said bit lines and to at least two of said word lines being used to select a ROM cell connected to said bit line, for producing an output signal indicative of a selection of said ROM cell connected to said bit line, based on word line select signals supplied on said at least two of said word lines.

An A/D converter comprising: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, said plurality of comparators including a first comparator performing a reset operation and a second comparator performing a comparison operation between an analog input voltage and an associated analog reference voltage to output an output signal, said first and second comparators operating in parallel in one converting cycle; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators, wherein said encoder includes: a plurality of word lines; a plurality of bit lines, at least two of said bit lines being assigned to a specific one of said digital output signals selected from said plurality of bits, a single one of said bit lines being assigned to each of the remaining digital output signals; a plurality of ROM cells located between said plurality of bit lines and said plurality of word lines, each of said ROM cells being responsive to a word line select signal supplied to the word line associated with said ROM cell for supplying a digital output signal; and a logic circuit, connected to said at least two of said bit lines, for obtaining an exclusive OR of digital signals on said at least two of said bit lines and for outputting therefrom the resultant signal as the specific one of said digital output signals.

An A/D converter comprising: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, each comparator performing a reset operation and a comparison operation between the analog input voltage and an associated analog reference voltage to output an output signal, said a plurality of comparators alternately performing said reset operation; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators, wherein said encoder includes: a plurality of ROM cells, connected between a plurality of bit lines and a plurality of word lines, each of said ROM cells being responsive to a word line select signal supplied to a word line associated with each of said ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of said ROM cells; and at least one logic processor, coupled to one of said bit lines and to at least two of said word lines being used to select a ROM cell connected to said bit line, for producing an output signal indicative of a selection of said ROM cell connected to said bit line, based on word line select signals supplied on said at least two of said word lines.

An A/D converter comprising: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, each comparator performing a reset operation and a comparison operation between the analog input voltage and an associated analog reference voltage to output an output signal, said a plurality of comparators alternately performing said reset operation; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators, wherein said encoder includes: a plurality of word lines; a plurality of bit lines, at least two of said bit lines being assigned to a specific one of said digital output signals selected from said plurality of bits, a single one of said bit lines being assigned to each of the remaining digital output signals; a plurality of ROM cells located between said plurality of bit lines and said plurality of word lines, each of said ROM cells being responsive to a word line select signal supplied to the word line associated with said ROM cell for supplying a digital output signal; and a logic circuit, connected to said at least two of said bit lines, for obtaining an exclusive OR of digital signals on said at least two of said bit lines and for outputting therefrom the resultant signal as the specific one of said digital output signals.

An A/D converter comprising: a reference voltage generating circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input signal and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation in which each comparator compares one of said reference voltages applied thereto with said analog input signal; an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators, wherein said encoder includes: a plurality of ROM cells, connected between a plurality of bit lines and a plurality of word lines, each of said ROM cells being responsive to a word line select signal supplied to a word line associated with each of said ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of said ROM cells; and at least one logic processor, coupled to one of said bit lines and to at least two of said word lines being used to select a ROM cell connected to said bit line, for producing an output signal indicative of a selection of said ROM cell connected to said bit line, based on word line select signals supplied on said at least two of said word lines; a control circuit coupled to said plurality of comparators for controlling said plurality of comparators so as to permit at least one of said comparators to perform the reset operation and to permit the remaining comparators to perform the comparison operation; a first selecting circuit controllable by said control circuit and provided between said plurality of comparators and said encoder for selectively supplying said encoder with the output signals of the comparators that are performing the comparison operation; and a second selecting circuit controllable by said control circuit and provided between said reference voltage generating circuit and said plurality of comparators for selectively distributing said plurality of analog reference voltages to said comparators.

An A/D converter comprising: a reference voltage generating circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input signal and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation in which each comparator compares one of said reference voltages applied thereto with said analog input signal; an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators, wherein said encoder includes: a plurality of word lines; a plurality of bit lines, at least two of said bit lines being assigned to a specific one of said digital output signals selected from said plurality of bits, a single one of said bit lines being assigned to each of the remaining digital output signals; a plurality of ROM cells located between said plurality of bit lines and said plurality of word lines, each of said ROM cells being responsive to a word line select signal supplied to the word line associated with said ROM cell for supplying a digital output signal; and a logic circuit, connected to said at least two of said bit lines, for obtaining an exclusive OR of digital signals on said at least two of said bit lines and for outputting therefrom the resultant signal as the specific one of said digital output signals; a control circuit coupled to said plurality of comparators for controlling said plurality of comparators so as to permit at least one of said comparators to perform the reset operation and to permit the remaining comparators to perform the comparison operation; a first selecting circuit controllable by said control circuit and provided between said plurality of comparators and said encoder for selectively supplying said encoder with the output signals of the comparators that are performing the comparison operation; and a second selecting circuit controllable by said control circuit and provided between said reference voltage generating circuit and said plurality of comparators for selectively distributing said plurality of analog reference voltages to said comparators.

An A/D converter comprising: a reference voltage generating circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input signal and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation in which each comparator compares one of said reference voltages applied thereto with said analog input signal, said plurality of comparators being adapted to produce a group of thermometer-code based output signals smaller by at least one in number than said comparators, wherein each of said comparators includes: a plurality of amplifying units; at least one capacitor provided between said plurality of amplifying units to connect said amplifying units in series; and an amplitude suppressing circuit, connected in parallel to one of said plurality of amplifying units, for suppressing an amplitude of an output signal of the one of said amplifying units; an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; a control circuit coupled to said plurality of comparators for controlling said plurality of comparators in such a way as to permit at least one of said comparators to perform the reset operation and to permit the remaining comparators to perform the comparison operation; a first selecting circuit controllable by said control circuit and provided between said plurality of comparators and said encoder for selectively supplying said encoder with the output signals of the comparators that are performing the comparison operation as said group of thermometer-code based output signals; and a second selecting circuit controllable by said control circuit and provided between said reference voltage generating circuit and said plurality of comparators, for selectively distributing said plurality of analog reference voltages to said comparators.

An A/D converter comprising: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation performed between the analog input voltage and an associated analog reference voltage, each comparator performing a plurality of comparison operations after performing the reset operation to output an output signal, wherein each of said comparators includes; a plurality of amplifying units; at least one capacitor provided between said plurality of amplifying units to connect said amplifying units in series; and an amplitude suppressing circuit, connected in parallel to one of said plurality of amplifying units, for suppressing an amplitude of an output signal of the one of said amplifying units; and an encoder for producing a digital signal consisting of a plurality of bite based on the output signals of said plurality of comparators.

An A/D converter comprising; a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, said plurality of comparators including a first comparator performing a reset operation and a second comparator performing a comparison operation between an analog input voltage and an associated analog reference voltage to output an output signal, said first and second comparators operating in parallel in one converting cycle, wherein each of said comparators includes: a plurality of amplifying units; at least one capacitor provided between said plurality of amplifying units to connect said amplifying units in series; and an amplitude suppressing circuit, connected in parallel to one of said plurality of amplifying units, for suppressing an amplitude of an output signal of the one of said amplifying units; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators.

An A/D converter comprising: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, each comparator performing a reset operation and a comparison operation between the analog input voltage and an associated analog reference voltage to output an output signal, said a plurality of comparators alternately performing said reset operation, wherein each of said comparators includes: a plurality of amplifying units; at least one capacitor provided between said plurality of amplifying units to connect said amplifying units in series; and an amplitude suppressing circuit, connected in parallel to one of said plurality of amplifying units, for suppressing an amplitude of an output signal of the one of said amplifying units; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators.

An A/D converter comprising: a reference voltage generating circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input signal and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation in which each comparator compares one of said reference voltages applied thereto with said analog input signal, wherein each of said comparators includes: a plurality of amplifying units; at least one capacitor provided between said plurality of amplifying units to connect said amplifying units in series; and an amplitude suppressing circuit, connected in parallel to one of said plurality of amplifying units, for suppressing an amplitude of an output signal of the one of said amplifying units; an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; a control circuit coupled to said plurality of comparators for controlling said plurality of comparators so as to permit at least one of said comparators to perform the reset operation and to permit the remaining comparators to perform the comparison operation; a first selecting circuit controllable by said control circuit and provided between said plurality of comparators and said encoder for selectively supplying said encoder with the output signals of the comparators that are performing the comparison operation; and a second selecting circuit controllable by said control circuit and provided between said reference voltage generating circuit and said plurality of comparators for selectively distributing said plurality of analog reference voltages to said comparators.

A semiconductor integrated circuit comprising: a prestage circuit for producing an analog signal; an A/D converter including: a reference voltage generating circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input signal and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation in which each comparator compares one of said reference voltages applied thereto with said analog input signal, said plurality of comparators being adapted to produce a group of thermometer-code based output signals smaller by at least one in number than said comparators; an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; a control circuit coupled to said plurality of comparators for controlling said plurality of comparators in such a way as to permit at least one of said comparators to perform the reset operation and to permit the remaining comparators to perform the comparison operation; a first selecting circuit controllable by said control circuit and provided between said plurality of comparators and said encoder for selectively supplying said encoder with the output signals of the comparators that are performing the comparison operation as said group of thermometer-code based output signals; and a second selecting circuit controllable by said control circuit and provided between said reference voltage generating circuit and said plurality of comparators, for selectively distributing said plurality of analog reference voltages to said comparators; and a poststage circuit for processing said digital signal.

A semiconductor integrated circuit comprising: a prestage circuit for producing an analog signal; an A/D converter including: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation performed between the analog input voltage and an associated analog reference voltage, each comparator performing a plurality of comparison operations after performing the reset operation to output an output signal; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; and a poststage circuit for processing said digital signal.

A semiconductor integrated circuit comprising: a prestage circuit for producing an analog signal; an A/D converter including: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, said plurality of comparators including a first comparator performing a rest operation and a second comparator performing a comparison operation between an analog input voltage and an associated analog reference voltage to output an output signal, said first and second comparators operating in parallel in one converting cycle; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; and a poststage circuit for processing said digital signal.

A semiconductor integrated circuit comprising: a prestage circuit for producing an analog signal; an A/D converter including: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, each comparator performing a reset operation and a comparison operation between the analog input voltage and an associated analog reference voltage to output an output signal, said a plurality of comparators alternately performing said reset operation; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; and a poststage circuit for processing said digital signal.

A semiconductor integrated circuit comprising: a prestage circuit for producing an analog signal; an A/D converter including: a reference voltage generating circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input signal and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation in which each comparator compares one of said reference voltages applied thereto with said analog input signal; an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; a control circuit coupled to said plurality of comparators for controlling said plurality of comparators so as to permit at least one of said comparators to perform the reset operation and to permit the remaining comparators to perform the comparison operation; a first selecting circuit controllable by said control circuit and provided between said plurality of comparators and said encoder for selectively supplying said encoder with the output signals of the comparators that are performing the comparison operation; and a second selecting circuit controllable by said control circuit and provided between said reference voltage generating circuit and said plurality of comparators for selectively distributing said plurality of analog reference voltages to said comparators; and a poststage circuit for processing said digital signal.

A semiconductor integrated circuit comprising: a prestage circuit for producing an analog signal; an A/D converter including: a reference voltage generating circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input signal and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation in which each comparator compares one of said reference voltages applied thereto with said analog input signal, said plurality of comparators being adapted to produce a group of thermometer-code based output signals smaller by at least one in number than said comparators; an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; a control circuit coupled to said plurality of comparators for controlling said plurality of comparators in such a way as to permit at least one of said comparators to perform the reset operation and to permit the remaining comparators to perform the comparison operation; a first selecting circuit controllable by said control circuit and provided between said plurality of comparators and said encoder for selectively supplying said encoder with the output signals of the comparators that are performing the comparison operation as said group of thermometer-code based output signals; and a second selecting circuit controllable by said control circuit and provided between said reference voltage generating circuit and said plurality of comparators, for selectively distributing said plurality of analog reference voltages to said comparators; an offset voltage canceling circuit for producing and outputting therefrom a digital signal for reducing an offset voltage supplied to said A/D converter from said prestage circuit, based on the digital signal output from said A/D converter, when the supply of said analog signal to said A/D converter from said prestage circuit is inhibited; and a D/A converter, connected to said prestage circuit and said offset voltage canceling circuit, for converting the digital output signal of said offset voltage canceling circuit to an analog signal, whereby an offset voltage is canceled by said analog signal supplied to said prestage circuit from said D/A converter.

A semiconductor integrated circuit comprising: a prestage circuit fur producing an analog signal; an A/D converter including: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation performed between the analog input voltage and an associated analog reference voltage, each comparator performing a plurality of comparison operations after performing the reset operation to output an output signal; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; an offset voltage canceling circuit for producing and outputting therefrom a digital signal for reducing an offset voltage supplied to said A/D converter from said prestage circuit, based on the digital signal output from said A/D converter, when the supply of said analog signal to said A/D converter from said prestage circuit is inhibited; and a D/A converter, connected to said prestage circuit and said offset voltage canceling circuit, for converting the digital output signal of said offset voltage canceling circuit to an analog signal, whereby an offset voltage is canceled by said analog signal supplied to said prestage circuit from said D/A converter.

A semiconductor integrated circuit comprising: a prestage circuit for producing an analog signal; an A/D converter including: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, said plurality of comparators including a first comparator performing a reset operation and a second comparator performing a comparison operation between an analog input voltage and an associated analog reference voltage to output an output signal, said first and second comparators operating in parallel in one converting cycle; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; an offset voltage canceling circuit for producing and outputting therefrom a digital signal for reducing an offset voltage supplied to said A/D converter from said prestage circuit, based on the digital signal output from said A/D converter, when the supply of said analog signal to said A/D converter from said prestage circuit is inhibited; and a D/A converter, connected to said prestage circuit and said offset voltage canceling circuit, for converting the digital output signal of said offset voltage canceling circuit to an analog signal, whereby an offset voltage is canceled by said analog signal supplied to said prestage circuit from said D/A converter.

A semiconductor integrated circuit comprising: a prestage circuit for producing an analog signal; an A/D converter including: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, each comparator performing a reset operation and a comparison operation between the analog input voltage and an associated analog reference voltage to output an output signal, said a plurality of comparators alternately performing said reset operation; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; an offset voltage canceling circuit for producing and outputting therefrom a digital signal for reducing an offset voltage supplied to said A/D converter from said prestage circuit, based on the digital signal output from said A/D converter, when the supply of said analog signal to said A/D converter from said prestage circuit is inhibited; and a D/A converter, connected to said prestage circuit and said offset voltage canceling circuit, for converting the digital output signal of said offset voltage canceling circuit to an analog signal, whereby an offset voltage is canceled by said analog signal supplied to said prestage circuit from said D/A converter.

A semiconductor integrated circuit comprising: a prestage circuit for producing an analog signal; an A/D converter including: a reference voltage generating circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input signal and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation in which each comparator compares one of said reference voltages applied thereto with said analog input signal; an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; a control circuit coupled to said plurality of comparators for controlling said plurality of comparators so as to permit at least one of said comparators to perform the reset operation and to permit the remaining comparators to perform the comparison operation; a first selecting circuit controllable by said control circuit and provided between said plurality of comparators and said encoder for selectively supplying said encoder with the output signals of the comparators that are performing the comparison operation; and a second selecting circuit controllable by said control circuit and provided between said reference voltage generating circuit and said plurality of comparators for selectively distributing said plurality of analog reference voltages to said comparators; an offset voltage canceling circuit for producing and outputting therefrom a digital signal for reducing an offset voltage supplied to said A/D converter from said prestage circuit, based on the digital signal output from said A/D converter, when the supply of said analog signal to said A/D converter from said prestage circuit is inhibited; and a D/A converter, connected to said prestage circuit and said offset voltage canceling circuit, for converting the digital output signal of said offset voltage canceling circuit to an analog signal, whereby an offset voltage is canceled by said analog signal supplied to said prestage circuit from said D/A converter.

A semiconductor integrated circuit device comprising: an amplifier for amplifying a read signal externally supplied as an analog signal; a filter for eliminating high-frequency signal components from an output signal of said amplifier; an A/D converter for converting an analog output signal of said filter to a digital signal, wherein said A/D converter includes: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation performed between the analog input voltage and an associated analog reference voltage, each comparator performing a plurality of comparison operations after performing the reset operation to output an output signal; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; and an equalizer, supplied with said digital signal output from said A/D converter, for adapting said digital signal to a circuit at subsequent stage.

A semiconductor integrated circuit device comprising: an amplifier for amplifying a read signal externally supplied as an analog signal; a filter for eliminating high-frequency signal components from an output signal of said amplifier; an A/D converter for converting an analog output signal of said filter to a digital signal, wherein said A/D converter includes: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, said plurality of comparators including a first comparator performing a reset operation and a second comparator performing a comparison operation between an analog input voltage and an associated analog reference voltage to output an output signal, said first and second comparators operating in parallel in one converting cycle; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; and an equalizer, supplied with said digital signal output from said A/D converter, for adapting said digital signal to a circuit at subsequent stage.

A semiconductor integrated circuit device comprising: an amplifier for amplifying a read signal externally supplied as an analog signal; a filter for eliminating high-frequency signal components from an output signal of said amplifier; an A/D converter for converting an analog output signal of said filter to a digital signal, wherein said A/D converter includes: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, each comparator performing a reset operation and a comparison operation between the analog input voltage and an associated analog reference voltage to output an output signal, said a plurality of comparators alternately performing said reset operation; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; and an equalizer, supplied with said digital signal output from said A/D converter, for adapting said digital signal to a circuit at subsequent stage.

A semiconductor integrated circuit device comprising: an amplifier for amplifying a read signal externally supplied as an analog signal; a filter for eliminating high-frequency signal components from an output signal of said amplifier; an A/D converter for converting an analog output signal of said filter to a digital signal, wherein said A/D converter includes: a reference voltage generating circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input signal and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation in which each comparator compares one of said reference voltages applied thereto with said analog input signal; an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; a control circuit coupled to said plurality of comparators for controlling said plurality of comparators so as to permit at least one of said comparators to perform the reset operation and to permit the remaining comparators to perform the comparison operation; a first selecting circuit controllable by said control circuit and provided between said plurality of comparators and said encoder for selectively supplying said encoder with the output signals of the comparators that are performing the comparison operation; and a second selecting circuit controllable by said control circuit and provided between said reference voltage generating circuit and said plurality of comparators for selectively distributing said plurality of analog reference voltages to said comparators; and an equalizer, supplied with said digital signal output from said A/D converter, for adapting said digital signal to a circuit at subsequent stage.

A recorded data reproducing apparatus comprising: a data reading device for reading data from a recording medium having a plurality of sectors, each sector having a servo area and a data area, and for outputting an analog data signal indicative of said read data; an A/D converter for converting said analog data signal to a digital signal, wherein said A/D converter includes: a reference voltage generating circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input signal and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation in which each comparator compares one of said reference voltages applied thereto with said analog input signal, said plurality of comparators being adapted to produce a group of thermometer-code based output signals smaller by at least one in number than said comparators; an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; a control circuit coupled to said plurality of comparators for controlling said plurality of comparators in such a way as to permit at least one of said comparators to perform the reset operation and to permit the remaining comparators to perform the comparison operation; a first selecting circuit controllable by said control circuit and provided between said plurality of comparators and said encoder for selectively applying said encoder with the output signals of the comparators that are performing the comparison operation as said group of thermometer-code based output signals; and a second selecting circuit controllable by said control circuit and provided between said reference voltage generating circuit and said plurality of comparators, for selectively distributing said plurality of analog reference voltages to said comparators; and a digital signal processing unit for subjecting said digital signal output from said A/D converting unit to digital processing.

A recorded data reproducing apparatus comprising: a data reading device for reading data from a recording medium having a plurality of sectors, each sector having a servo area and a data area, and for outputting an analog data signal indicative of said read data; an A/D converter for converting said analog data signal to a digital signal, wherein said A/D converter includes: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation performed between the analog input voltage and an associated analog reference voltage, each comparator performing a plurality of comparison operations after performing the reset operation to output an output signal; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; and a digital signal processing unit for subjecting said digital signal output from said A/D converting unit to digital processing.

A recorded data reproducing apparatus comprising: a data reading device for reading data from a recording medium having a plurality of sectors, each sector having a servo area and a data area, and for outputting an analog data signal indicative of said read data; an A/D converter for converting said analog data signal to a digital signal, wherein said A/D converter includes: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, said plurality of comparators including a first comparator performing a reset operation and a second comparator performing a comparison operation between an analog input voltage and an associated analog reference voltage to output an output signal, said first and second comparators operating in parallel in one converting cycle; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; and a digital signal processing unit for subjecting said digital signal output from said A/D converting unit to digital processing.

A recorded data reproducing apparatus comprising: a data reading device for reading data from a recording medium having a plurality of sectors, each sector having a servo area and a data area, and for outputting an analog data signal indicative of said read data; an A/D converter for converting said analog data signal to a digital signal, wherein said A/D converter includes: a reference voltage generator circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input voltage and said analog reference voltages respectively, each comparator performing a reset operation and a comparison operation between the analog input voltage and an associated analog reference voltage to output an output signal, said a plurality of comparators alternately performing said reset operation; and an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; and a digital signal processing unit for subjecting said digital signal output from said A/D converting unit to digital processing.

A recorded data reproducing apparatus comprising: a data reading device for reading data from a recording medium having a plurality of sectors, each sector having a servo area and a data area, and for outputting an analog data signal indicative of said read data; an A/D converter, for converting said analog data signal to a digital signal, wherein said A/D converter includes: a reference voltage generating circuit for producing a plurality of different analog reference voltages; a plurality of comparators supplied with an analog input signal and said analog reference voltages respectively, each comparator being switchable between a reset operation and a comparison operation in which each comparator compares one of said reference voltages applied thereto with said analog input signal; an encoder for producing a digital signal consisting of a plurality of bits based on the output signals of said plurality of comparators; a control circuit coupled to said plurality of comparators for controlling said plurality of comparators so as to permit at least one of said comparators to perform the reset operation and to permit the remaining comparators to perform the comparison operation; a first selecting circuit controllable by said control circuit and provided between said plurality of comparators and said encoder for selectively supplying said encoder with the output signals of the comparators that are performing the comparison operation; and a second selecting circuit controllable by said control circuit and provided between said reference voltage generating circuit and said plurality of comparators for selectively distributing said plurality of analog reference voltages to said comparators; and a digital signal processing unit for subjecting said digital signal output from said A/D converting unit to digital processing.