US Patent 5,719,439 — Semiconductor package integral with semiconductor chip

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Abstract

A semiconductor chip having a semiconductor substrate, a plurality of pads formed above the semiconductor substrate a first passivating film formed over an entire surface of the semiconductor substrate, and having openings above the pads the surface of the first passivating film being flat, a plurality of interconnection lines formed on the surface of the first passivating film, a second passivating film formed over the entire surface of the first passivating film and having through holes, the through holes being arranged in the form of an array, the surface of the second passivating film being flat, a plurality of contacts for connection to external leads each of the contacts being formed within and above a respective one of the through holes, the contacts being arranged in the form of an array.

Claims

65 · 4 independent · depth 2

65 granted claims

›1.independentA semiconductor package comprising: a semiconductor chip having a semiconductor substrate, a plurality of pads formed above said semiconductor substra…+15

›2.↳ 1The semiconductor package according to claim 1, wherein said plurality of pads is placed along the edges of said semiconductor substrate.d2

›3.↳ 1The semiconductor package according to claim 1, wherein said plurality of pads is placed evenly over the entire surface of said semiconductor substrat…d2

›4.↳ 1The semiconductor package according to claim 1, wherein the edges of said semiconductor substrate coincide with the edges of said first passivating fi…d2

›5.↳ 1The semiconductor package according to claim 1, wherein each of said interconnection lines is made of one of conductors including aluminum and copper.d2

›6.↳ 1The semiconductor package according to claim 1, wherein said second passivating film functions as a package and has a thickness in the range of 0.05 t…d2

›7.↳ 1The semiconductor package according to claim 1, wherein the edges of said second passivating film are rounded off.d2

›8.↳ 1The semiconductor package according to claim 1, wherein each of said first and second passivating films is made of one of insulating materials includi…d2

›9.↳ 1The semiconductor package according to claim 1, wherein, when viewed from above said semiconductor substrate, said contacts are placed symmetrically w…d2

›10.↳ 1The semiconductor package according to claim 1, wherein said contacts are placed evenly over the entire surface of said second passivating film.d2

›11.↳ 1The semiconductor package according to claim 1, wherein said contacts are placed along the edges of said second passivating film.d2

›12.↳ 1The semiconductor package according to claim 1, wherein, when viewed from above said semiconductor substrate, each of said contacts has a circular sha…d2

›13.↳ 1The semiconductor package according to claim 1, wherein, when viewed from above said semiconductor substrate, said semiconductor substrate has a squar…d2

›14.↳ 1The semiconductor package according to claim 1, wherein each of said contacts is made of one of conductors including copper, gold, nickel, and a two-l…d2

›15.↳ 1The semiconductor package according to claim 1, further comprising solder balls each formed on a respective one of said contacts.d2

›16.↳ 1The semiconductor package according to claim 1, wherein a bottom surface of the semiconductor package comprises a bottom surface of the semiconductor …d2

›17.independentA semiconductor package comprising: a semiconductor chip having a semiconductor substrate, a plurality of pads formed above said semiconductor substra…+15

›18.↳ 17The semiconductor package according to claim 17, wherein said plurality of pads is placed along the edges of said semiconductor substrate.d2

›19.↳ 17The semiconductor package according to claim 17, wherein said plurality of pads is placed evenly over the entire surface of said semiconductor substra…d2

›20.↳ 17The semiconductor package according to claim 17, wherein the edges of said semiconductor substrate coincide with the edges of said second passivating …d2

›21.↳ 17The semiconductor package according to claim 17, wherein each of said interconnection lines is made of one of conductors including aluminum and copper…d2

›22.↳ 17The semiconductor package according to claim 17, wherein said second passivating film functions as a package and has a thickness in the range of 0.05 …d2

›23.↳ 17The semiconductor package according to claim 17, wherein the edges of said second passivating film are rounded off.d2

›24.↳ 17The semiconductor package according to claim 17, wherein each of said first and second passivating films is made of one of insulating materials includ…d2

›25.↳ 17The semiconductor package according to claim 17, wherein, when viewed from above said semiconductor substrate, said contacts are placed symmetrically …d2

›26.↳ 17The semiconductor package according to claim 17, wherein said contacts are placed evenly over the entire surface of said second passivating film.d2

›27.↳ 17The semiconductor package according to claim 17, wherein said contacts are placed along the edges of said second passivating film.d2

›28.↳ 17The semiconductor package according to claim 17, wherein, when viewed from above said semiconductor substrate, each of said contacts has a circular sh…d2

›29.↳ 17The semiconductor package according to claim 17, wherein, when viewed from above said semiconductor substrate, said semiconductor substrate has a squa…d2

›30.↳ 17The semiconductor package according to claim 17, wherein each of said contacts is made of one of conductors including copper, gold, nickel, and a two-…d2

›31.↳ 17The semiconductor package according to claim 17, further comprising solder balls each formed on a respective one of said contacts.d2

›32.↳ 17The semiconductor package according to claim 17, wherein a bottom surface of the semiconductor package comprises a bottom surface of the semiconductor…d2

›33.independentA semiconductor package comprising: a semiconductor chip having a semiconductor substrate, a plurality of pads formed above said semiconductor substra…+15

›34.↳ 33The semiconductor package according to claim 33, wherein said plurality of pads is placed along the edges of said semiconductor substrate.d2

›35.↳ 33The semiconductor package according to claim 33, wherein said plurality of pads is placed evenly over the entire surface of said semiconductor substra…d2

›36.↳ 33The semiconductor package according to claim 33, wherein the edges of said semiconductor substrate coincide with the edges of said second passivating …d2

›37.↳ 33The semiconductor package according to claim 33, wherein each of said interconnection lines is made of one of conductors including aluminum and copper…d2

›38.↳ 33The semiconductor package according to claim 33, wherein said second passivating film functions as a package and has a thickness in the range of 0.05 …d2

›39.↳ 33The semiconductor package according to claim 33, wherein the edges of said second passivating film are rounded off.d2

›40.↳ 33The semiconductor package according to claim 33, wherein each of said first and second passivating films is made of one of insulating materials includ…d2

›41.↳ 33The semiconductor package according to claim 33, wherein, when viewed from above said semiconductor substrate, said contacts are placed symmetrically …d2

›42.↳ 33The semiconductor package according to claim 33, wherein said contacts are placed evenly over the entire surface of said second passivating film.d2

›43.↳ 33The semiconductor package according to claim 33, wherein said contacts are placed along the edges of said second passivating film.d2

›44.↳ 33The semiconductor package according to claim 33, wherein, when viewed from above said semiconductor substrate, each of said contacts has a circular sh…d2

›45.↳ 33The semiconductor package according to claim 33, wherein, when viewed from above said semiconductor substrate, said semiconductor substrate has a squa…d2

›46.↳ 33The semiconductor package according to claim 33, wherein each of said contacts is made of one of conductors including copper, gold, nickel, and a two-…d2

›47.↳ 33The semiconductor package according to claim 33, further comprising solder balls each formed on a respective one of said contacts.d2

›48.↳ 33The semiconductor package according to claim 33, wherein a bottom surface of the semiconductor package comprises a bottom surface of the semiconductor…d2

›49.independentA semiconductor package comprising: a semiconductor chip having a semiconductor substrate, a plurality of pads formed above said semiconductor substra…+16

›50.↳ 49The semiconductor package according to claim 49, wherein said plurality of pads is placed along the edges of said semiconductor substrate.d2

›51.↳ 49The semiconductor package according to claim 49, wherein said plurality of pads is placed evenly over the entire surface of said semiconductor substra…d2

›52.↳ 49The semiconductor package according to claim 49, wherein the edges of said semiconductor substrate are inside the edges of said second passivating fil…d2

›53.↳ 49The semiconductor package according to claim 49, wherein each of said interconnection lines is made of one of conductors including aluminum and copper…d2

›54.↳ 49The semiconductor package according to claim 49, wherein said second passivating film functions as a package and has a thickness in the range of 0.05 …d2

›55.↳ 49The semiconductor package according to claim 49, wherein the edges of said second passivating film are rounded off.d2

›56.↳ 49The semiconductor package according to claim 49, wherein each of said first and second passivating films is made of one of insulating materials includ…d2

›57.↳ 49The semiconductor package according to claim 49, wherein, when viewed from above said semiconductor substrate, said contacts are placed symmetrically …d2

›58.↳ 49The semiconductor package according to claim 49, wherein said contacts are placed evenly over the entire surface of said second passivating film.d2

›59.↳ 49The semiconductor package according to claim 49, wherein said contacts are placed along the edges of said second passivating film.d2

›60.↳ 49The semiconductor package according to claim 49, wherein, when viewed from above said semiconductor substrate, each of said contacts has a circular sh…d2

›61.↳ 49The semiconductor package according to claim 49, wherein, when viewed from above said semiconductor substrate, said semiconductor substrate has a squa…d2

›62.↳ 49The semiconductor package according to claim 49, wherein said metal layer is made of at least one of metals including titanium, nickel, and palladium.d2

›63.↳ 49The semiconductor package according to claim 49, wherein each of said contacts is made of one of conductors including copper, gold, nickel, and a two-…d2

›64.↳ 49The semiconductor package according to claim 49, further comprising solder balls each formed on a respective one of said contacts.d2

›65.↳ 49The semiconductor package according to claim 49, wherein a bottom surface of the semiconductor package comprises a bottom surface of the semiconductor…d2

Classifications

10 codes

USPC · US Patent Classification

257/690257/760257/766257/758257/786257/780257/750257/700257/701257/773

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Examiner

Wael Fahmy

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Citations: 6 back · 4 forward

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