High-Q inductors in silicon technology without expensive metalization

1. Field of the Invention

The present invention generally relates to the design and construction of electrical inductors and, more particularly, to a novel monolithic inductor structure which is compatible with a low-cost silicon technology.

2. Description of the Prior Art

Miniaturization of electronic circuits is a goal in virtually every field, not only to achieve compactness in mechanical packaging, but also to decrease the cost of manufacture of the circuits. Many digital and analog circuits, including complex microprocessors and operational amplifiers, have been successfully implemented in silicon based integrated circuits (ICs). These circuits typically include active devices such as bipolar transistors and field effect transistors (FETs), diodes of varies types, and passive devices such as resistors and capacitors.

One area that remains a challenge to miniaturize are radio frequency (RF) circuits, such as those used in cellular telephones, wireless modems, and other types of communication equipment. The problem is the difficulty in producing a good inductor in silicon technologies that is suitable for RF applications. Attempts to integrate inductors into silicon technologies have yielded either inductor Q values less than five or required special metalization layers such as gold.

It is well known that the direct current (DC) resistance of a metal line that forms a spiral inductor is a major contributor to the inductor Q degradation. One way to reduce this effect is to use wide metal line-widths, however, this increases the inductor area and the parasitic capacitance associated with the structure. The larger inductor area limits the miniaturization that can be achieved, and the parasitic capacitance associated with the larger area decreases the self-resonance frequency of the inductor, thereby limiting its useful frequency range. Also, since the Q is directly proportional to frequency and inversely proportional to the series loss of the inductor, the metal line widths cannot be chosen arbitrarily large.

It is therefore an object of the present invention to provide a novel monolithic high-Q inductor structure in silicon technology.

According to the invention, there is provided a high Q inductor structure formed with multiple metalization levels in a conventional integrated circuit technology in which inductor turns utilize these multiple levels to reduce the inductor resistance. Inductors with Q values above five can be integrated with this approach at radio and microwave frequencies.

The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:

FIG. 1 is a plan view of a spiral inductor structure with three levels of metal according to the invention;

FIG. 2 is a cross section of a spiral line segment;

FIG. 3 is a cross-section of inductor showing the cross-under design used to connect to the center terminal of spiral; and

FIG. 4 is a graph showing the frequency spectrum of an oscillator using the inductor shown in FIGS. 1, 2 and 3.

Referring now to the drawings, and more particularly to FIG. 1, there is shown a plan view of the spiral inductor structure according to the preferred embodiment of the invention. As shown in FIGS. 2 and 3, this structure has three levels of metal, the first metal level 1 being the first level above a layer silicon oxide 2 on a silicon substrate 3. See FIG. 3. The first metal level 1 is covered by a second layer of silicon dioxide 4 through which a via 5 is formed. The first metal level 1 is used as a cross-under to make connection to the central terminal 6 (FIG. 1) of the spiral structure. The via 5 is filed with a metal to interconnect the first level with the second metal level 7. This next level 7 is covered by a third silicon dioxide layer 8 having a plurality of vias 9 formed therein. As shown in FIG. 2, the vias 9 are filled with a metal to interconnect the second metal level 7 to a third metal level 10. The two metal levels 7 and 10 are identical spiral metal patterns, as shown in FIGS. 1 and 3, and the vias 9 effectively shunt the two metal levels. Thus, two layers are used for inductor turns, and these two layers provide two inductors connected in parallel to reduce DC resistance. The reduction in DC resistance for a two layer inductor is at least a factor of two, hence providing a large Q enhancement. Obviously, the DC resistance can be further decreased by shunting more metal layers if extra wiring levels are offered by the technology.

This approach solves the problem of inductor design for high frequency (into the GHz range) applications by employing multiple layers of metal connected with via holes through the isolation levels. Most of the silicon technologies at present have at least three or more metal layers for wiring the circuits. The first metal level has to be used as a cross-under to make a connection to the circled terminal of the spiral structure, as shown in FIG. 1, thus leaving at least two layers to be used for the inductor turns. This invention has been implemented in hardware using a mature BiCMOS (bipolar/complementary metal oxide semiconductor) technology.

In a specific example, the measured Q of a four-turn spiral inductor was at least seven at 2.4 Ghz. This inductor uses two metal levels to implement the turns and a third one for the cross under. The inductor performed well as part of a resonator in a 2.4 GHz Colpitts bipolar oscillator, as shown in FIG. 4.

While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.