Paged memory scheme

The present invention is directed to a method and apparatus for accessing a portion of a memory space. More particularly, the present invention provides a method and apparatus for efficiently addressing a memory with a limited number of available address pins.

In read and write operations in a computer memory, an address is used which has enough possible unique values to correspond to any one of the available addressable locations in the memory space. For instance a 64 Kbyte RAM will require an address having at least a 16-bit length to allow direct access to each memory location.

A known microprocessor, e.g. an Intel® 8086 microprocessor, can utilize a multiplexed address and data bus so that a certain number of pins are shared by address and data transmissions. In the known system, every bus cycle comprises an address phase, where the address is strobed into a latch and a data phase, where the data is written to or read from a memory. Though efficient in using pins, this method of supplying an address on a limited number of pins is slow.

A known method for increasing the number of addressable locations that can be accessed with an address having a length that is less than the number of bits required for the memory space is referred to as paging. In a paging scheme, a first unique address value is generated to define a "page" of the memory. A second unique address value, called an offset, is then generated to specify an addressable location in the selected page. Paging becomes necessary when an application requires a larger address space than was originally anticipated or when insufficient addressing pins are available for transmitting an address off a chip.

Paging can be implemented in a variety of ways. For instance, it can be controlled by software by writing an address to an output device to select the appropriate page, then data can be read from or written to the selected page. Paging can also be implemented in hardware where a device recognizes that an address is not in the currently selected address space and changes the page accordingly.

There is, therefore, a need for an addressing scheme that allows for efficient access of memory using a limited address length or an economical number of pins for address transmission.

The present invention is directed to an apparatus and method for supplying a limited number of address bits, e.g., via a limited number of pins on a chip. Those address bits that can be placed at the pins are directly coupled to an external memory device. The remaining address bits are stored in a memory device such as a register or latch having an output coupled to the external memory device. The latch can be arranged external to the chip so that the address bits provided by the latch do not use any pins of the chip.

The address bits stored in the latch can be loaded through shared pins of the chip, as, e.g., certain ones of the pins used to transmit data on and off the chip. The address bits to be stored in the latch are coupled to an input of a multiplexing device. The data bits are coupled to the other input of the multiplexing device. The latch has its input coupled to the output of the multiplexing device.

In accordance with a feature of the present invention, the latch is arranged to store a default page value which specifies a default page within the external memory device. At initialization time (e.g. at reset), a paging cycle is executed wherein the default page value is selected and latched into the latch. On the processor chip, the high order bits of a current address are compared to the default page value. On a match, a control device selects the data bits at the multiplexing device and a read or write operation follows quickly. If there is no match, a paging cycle is executed where the high order bits of the address are selected at the multiplexing device and latched through the latch. Then, the control device selects the data bits at the multiplexing device and the read or write operation follows. Finally, a second paging cycle is performed to restore the default page value to the latch.

If the default page value corresponds to the most frequently accessed page of the memory, the processing time for the paging cycle is saved for each memory access to that page for more efficient read and write operations within the busiest portion of the memory.

FIG. 1A is a block diagram of a known circuit performing an example of a paged memory scheme for supplying address and data information to an external memory device.

FIG. 1B is a timing diagram for the circuit of FIG. 1A.

FIG. 2A is a block diagram of a circuit for supplying address and data information to an external memory device constructed according to an embodiment of the present invention.

FIGS. 2B and 2C are timing diagrams for the circuit of FIG. 2A.

FIG. 3 is a block diagram of a circuit for supplying address and data information to an external memory device constructed according to a further embodiment of the present invention.

Referring to FIG. 1A, an example of a known paged memory system is shown. In this example, only thirteen pins are available to address 64 Kwords. Using twelve pins for an address allows access to 4,096 locations (i.e., 2 12 =4,096). The thirteenth pin could be used as a latch enable for high order bits of the address. As illustrated in FIG. 1A, an incoming address is split into a string of twelve bits and a string of four bits. The string of four bits is coupled to a multiplexing device 11. The string of twelve bits is coupled directly to an address input of an external memory device 13 via the twelve available pins. A control device 15 controls the operation of the multiplexing device 11 in an interface 17 between the incoming address and data lines and the external memory device 13. The control device 15 also provides an address latch enable signal to a register or latch 19 and a read/write control signal to the external memory device 13. In this example, the external memory device 13 is a 64 Kword memory.

In operation, the control device 15 will select the appropriate writing or reading function with a read/write control signal. The control device 15 will also select the string of four bits of the address at the multiplexing device 11. These four bits will then be latched and supplied to the address input of the external memory device 13. Then, the control device 15 will select the incoming data string at the multiplexing device 11 which allows this data string to be supplied to the data input of the external memory device 13.

If the twelve bit string represents the low order bits of an address, they will actually point to a 4 Kword offset in a page of memory in the external memory device 13. Therefore, there is a delay in the arrangement of FIG. 1A in that a paging cycle occurs in order to supply the appropriate page address (i.e., the four high order bits of the address) to the latch 19. The timing of the arrangement of FIG. 1A is shown in FIG. 1B.

Referring to FIG. 2A, a block diagram of a circuit performing the paged addressing scheme of the present invention is shown. A register or latch 21 is used as an external page register supplying the four high order address bits for a 4 Kword page of memory. In order to avoid the paging cycle seen in FIGS. 1A and 1B for access to a certain preselected area of memory, the four bits appearing at the output of the latch 21 are set to a default value which points to the most accessed 4 Kword page of memory in an external memory device 23. During initialization, a single paging cycle is used to load the default value in the latch 21.

An interface 25 between the incoming system address and data lines and the external memory device 23 comprises a multiplexing device 27, a comparator 29, and a control device 31. The control device 31 controls the operation of the external memory device 23 via a read/write control line. The control device 31 also controls the operation of the latch 21 with an address latch enable line and the multiplexing device 27. The comparator 29 has two inputs, one of which is coupled to the four high order bits of the incoming address. The second input of the comparator 29 is set to the default string of four bits. The comparator 29 is coupled to the control device 31 to provide an indication to the control device 31 of the comparison between the high order bits input to the comparator 29 and the default value.

When a read or write operation is to be performed, the appropriate binary values will appear on the incoming address and data lines. The twelve low order bits of the address are coupled directly to the address input of the external memory device 23 via twelve pins available for use as address pins. The four high order bits of the incoming address are coupled directly to the multiplexing device 27 and the first input of the comparator 29.

If the comparator 29 determines that the four high order bits of the address are equal to the default page setting, the control device 31 responds by enabling the requested read or write operation at the external memory device via the read/write control line. The latch 21 provides for the immediate and direct input of the high order default page value to the memory device 23. The control device 31 will also select the data lines at the multiplexing device 27. As seen in FIG. 2B, the address and data information are quickly processed for all read and write operations using the default page.

If the comparator 29 determines that the four high order bits of the incoming address are not equal to the default setting, the control device 31 responds by selecting the four high order address lines at the multiplexing device 27. The control device 31 will then send an address latch enable signal to the latch 21 in order to couple the appropriate binary values of the high order address bits input to the multiplexing device 27 to the address input of the external memory device 23.

Once the four high order bits of the address are latched, the control device 31 will select the data lines at the multiplexing device 27. The appropriate read/write operation at the external memory device 23 will then be initiated by the control device 31 via the read/write control line.

When the read/write operation is completed, the default value is resupplied to the latch 21. In the embodiment illustrated in FIG. 2A, after a read to a non-default page, the control device 31 will select a default page line at the multiplexing device 27. The control device 31 will then send an address latch enable signal to the latch 21 in order to latch the binary values of the default page bits input to the multiplexing device 27 into the latch 27. The timing diagram for such non-default read/write operations is illustrated in FIG. 2C.

An alternative embodiment of the present invention is shown in FIG. 3. In the illustrated embodiment, the default page value is set to four binary zero values. After a read or write to a non-default page, the control device 31 asserts a reload -- default signal which causes the latch signal output to be reset to the binary 0 values. In this manner, the default page value, binary 0, is reloaded into the latch 21 after a read/write operation to a non-default page. The use of binary zeros for the default page value simplifies the system in that the default page value can be conveniently reloaded into the latch 21 by resetting the latch 21 to zero.

It will be appreciated by one having ordinary skill in the art that many variations of the present invention can be realized. The paged memory scheme can be set up for different address lengths and the default page setting can be programmably changed. Also, the extended address space which is produced via the paged memory scheme can be encoded in a known manner to select and address multiple physical memory devices.