USPatentGranted
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Non-volatile semiconductor memory with CVD tunnel oxide

Granted 16 Jun 1992 · no office action yet

Application
241752
filed 7 Sep 1988
Publication
Not published
not published
Patent· this page
US 5,122,847
granted 16 Jun 1992

Life of the patent

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Abstract

A non-volatile semiconductor memory device is comprised of a floating gate electrode disposed on and electrically insulated from a semiconductor substrate for storing electric charge. A tunnel insulating film is disposed in contact with the floating gate electrode to inject and extract the electric charge to and from the floating gate electrode in the form of an electric tunnel current flowing through the tunnel insulating film. The tunnel insulating film is composed of silicon oxide chemically-vapor-deposited at a temperature between 700.degree. C. and 900.degree. C. from the vapor mixture of dichlorosilane and dinitrogen monoxide on the order of 100 .ANG. thickness to thereby establish a breakdown current density more than 1.0 A/cm.sup.2.

Description

5 parts
›This is a continuation of application Ser. No…

This is a continuation of application Ser. No. 905,924, filed Sept. 10, 1986, now abandoned.

›BACKGROUND OF THE INVENTION

The present invention provides a floating gate type EEPROM which employs a CVD insulator film as a tunnel oxide film through which electric charge is transferred between a floating gate electrode and another electrode, thereby enabling larger number of times of writing and erasing operations than that in the case of a conventional floating gate type EEPROM which employs a thermally oxidized film as the tunnel oxide film.

1. Field of the Invention

The present invention relates to an electrically erasable and programmable floating gate type non-volatile semiconductor memory which enables electrical writing and erasing operation to be readily effected.

2. Description of the Prior Art

The prior art shows at least, a floating gate type EEPROM, for example, the following patent U.S. Pat. No. 4,203,158 - Dov. Frohman-Bentchkowsky. et al. -May 13, 1980.

FIG. 2 is a sectional view of a conventional floating gate type EEPROM. On the surface of the P-type semiconductor substrate 11, there are provided the N + type source area 12 and the drain area 13, above which is provided the oxidized gate film 14. In the small are adjacent to the drain area 13, there is provided the thin oxidized film 15, above which are provided the floating gate electrode 16, the second oxidized gate film 17 and the control gate electrode 18. Writing operation is conducted by applying a writing voltage to the control gate electrode 18, so that the electrons are injected from the drain area 13 into the floating gate electrode 16 through the thin oxidized film 15. Erasing operation is conducted by applying an erasing voltage to the control gate electrode 18, so that the electrons are extracted from the floating gate electrode 16 into the drain area 13 through the thin oxidized film 15. Writing and erasing operations in the floating gate type EEPROM are effected by means of Fowler-Nordheim tunnel current flowing through a thin oxide film (100 to 150Å). This thin oxide film for writing and erasing operations has heretofore been constituted by a thermally oxidized film.

The thermally oxidized film 15 conventionally employed for writing and erasing has, however, the disadvantage that breakdown occurs when the number of times of writing and erasing operations reaches about 10 4 .

›SUMMARY OF THE INVENTION

To solve the above-described problem, the present invention employs a CVD insulator film as an insulator film for writing and erasing operations in place of the thermally oxidized film. It has heretofore been considered that CVD insulator film is inferior to thermally oxidized film in terms of characteristics, e.g., a lower density and a larger leakage current. However, it has been found that a CVD oxide film which is formed at a high temperature, i.e., 700° C. or higher, has superior characteristics to those of thermally, oxidized film.

More specifically, such a CVD insulator film exhibits excellent characteristics when used as a thin insulation film on the order of 100Å, namely, the CVD insulator film has a large breakdown current density and is not readily broken down in contrast to the thermally oxidized film. Thus, the present invention employs this CVD insulator film as a tunnel insulator film.

The CVD insulator film as an insulator film for writing and erasing in a floating gate type EEPROM as described above enables the EEPROM to carry out an increased number of times of writing and erasing operations, i.e., about 10 6 , which is more than 100 times that in the case of the prior art EEPROM.

›BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of floating gate type EEPROM in accordance with a first embodiment of the present invention;

FIG. 2 is a sectional view of a conventional floating gate type EEPROM;

FIG. 3 is a sectional view of a floating gate type EEPROM in accordance with a second embodiment of the present invention;

FIG. 4 shows the respective rewriting characteristics of the EEPROM according to the present invention which employs a CVD insulator film and the conventional EEPROM which employs a thermally oxidized film; and

FIG. 5 shows the respective breakdown current densities of the CVD insulator film and the thermally oxidized film.

›DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention will be described hereinunder by way of embodiments thereof. FIG. 1 is a sectional view of a floating gate type EEPROM in accordance with a first embodiment of the present invention.

On the surface of a P-type semiconductor substrate 1, N + -type source region 2 and N + -type drain region 3 are formed in spaced relation, and a first insulating film in the form of a gate oxide film 4 is provided thereon. A tunnel insulating film in the form of a chemically-vapor-deposited or CVD insulator film 5 of 100Å thickness is provided on a small region in contact with the drain region 3 and a floating gate electrode 6, a second insulating film in the form of a gate oxide film 7 and a control gate electrode 8 are provided in that order on the CVD insulator film 5.

Writing operation is conducted by applying a writing voltage to the control gate electrode 8, so that the electrons are injected from the drain region 3 into the floating gate electrode 6 in the form of a tunnel current flowing through the CVD insulating film 5.

Erasing operation is conducted by applying an erasing voltage to the control gate electrode 8, so that the electrons are extracted from the floating gate electrode 6 into the drain region 3 through the CVD insulation film 5.

The CVD insulator film 5 is formed in such a manner that the vapor mixture of dischlorosilane (SiH 2 Cl 2 ) and nitrous oxide or dinitrogen monoxide (N 2 O) is employed and a silicone moxide film is formed as a single layer under a vacuum at a temperature of 700° to 900° C. This single-layered CVD insulator film 5 exhibits excellent characteristics as a thin insulating film on the order of 100Å, namely, it has a single-layered large breakdown current density and is not readily broken down in contrast to the thermally oxidized film 15. It is therefore possible to greatly increase the number of times of available writing and erasing operations.

It should be noted that, although CVD oxide film is employed as the CVD insulator film 5 in this embodiment, CVD oxide film is not necessarily limitative.

FIG. 4 shows the respective rewriting characteristics of the floating gate type EEPROM in accordance with the first embodiment which employs a CVD insulator film and the conventional EEPROM which employs a thermally oxidized film. In the graph shown in FIG. 4, the number of times of writing and erasing operations is plotted along the axis of abscissas and the voltage value (V TH ) is plotted along the axis of ordinates. It will be understood from FIG. 4 that the EEPROM which employs the CVD insulator film 5 is relatively durable and breaks down when the number of times of writing and erasing operations reaches about 10 6 , whereas the EEPROM which employs the thermally oxidized film 15 breaks down when the number of times of writing and erasing operations reached about 10 4 . The EEPROM according to the present invention has less change in the voltage value and therefore exhibits high reliability.

The reason for this will be explained below. FIG. 5 shows the respective breakdown current densities of the CVD insulator film 5 and the thermally oxidized film 15. In the graph shown in FIG. 5, the thickness of the oxide films is plotted along the axis of abscissas and the breakdown current ,density is plotted along the axis of ordinates. In FIG. 5 the marks means as follows;

◯. . . breakdown current A of the CVD insulator film 5 when the gate voltage V g is positive.

Δ. . . breakdown current B of the CVD insulator film 5 when the gate voltage V g is negative.

. . . breakdown current C of the thermally oxidized film 15 when the gate voltage V g is positive.

. . breakdown current D of the thermally oxidized film 15 when the gate voltage V g is negative.

It will be understood from FIG. 5 that the CVD insulator film 5 exhibits a larger breakdown current density than that of the thermally oxidized film 15. Accordingly, the CVD insulator film 5 enables the number of times of available writing and erasing operations increased by a large margin in contrast to the thermally oxidized film 15.

FIG.3 is a sectional view of a floating gate type EEPROM in accordance with a second embodiment of the present invention.

On the surface of a P-type semiconductor substrate 21, N + -type source and drain regions 22, 23 are formed, and a first gate oxide film 24 and a floating gate electrode 26 are provided over the space between the source and drain regions 22 and 23. In addition, a Second gate oxide film 27 and a control gate electrode 28 are provided on the left-hand portion of the floating gate electrode 26, while a CVD insulator film 25 of 100Å thickness and an electrode 29 are provided on the exposed right-hand portion of the floating gate electrode 26. The electrode 29 is electrically connected to the floating gate electrode to transfer electric charge between the electrode 29 and the floating gate electrode 26. Writing operation is conducted by applying a writing voltage to the control gate electrode 28 opposite to the writing and erasing electrode 29, so that the electrons are injected from the writing and erasing electrode 29 into the floating gate electrode 26 through the CVD insulator film 25. Erasing operation is conducted by applying an erasing voltage to the control gate electrode 28, so that the electrons stored in the floating gate electrode 26 are extracted from the floating gate electrode 26 into the writing and erasing electrode 29 through the CVD insulating film 25.

In this embodiment, the floating gate electrode 26 below the CVD insulator film 25 can be formed of polycrystalline silicon. In such case also, the EEPROM which employs the CVD insulator film 25 enables the number, of times of available writing and erasing operations to be increased by a large margin as compared with the conventional EEPROM which employs the thermally oxidized film, in a manner similar to that in the case of the first embodiment.

As will be clearly understood from the above description, the present invention employs the CVD insulator film 5 as a tunnel insulating film of a floating gate type EEPROM and thereby offers the advantage that the number of times of available writing and erasing operations can be increased so as to be about 100 times that in the case of the prior art EEPROM which employs the thermally oxidized film 15. Accordingly, the present invention can provide a highly reliable floating gate type EEPROM.

1 of 5 part labels are ours — the grant heads the rest

Claims

13 · 2 independent · depth 5
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13 granted claims

Classifications

6 codes
IPC · International Patent Classification
Section H — Electricity
  • H01L29/788
  • H01L29/792
  • H01L21/8247
USPC · US Patent Classification
357/23.5437/238357/6

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Pendency
3.8 y
1,378 days filing → grant
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Examiner
Jerome Jackson, Jr.
art unit 253 · TC 2500
Citations: 16 back · 5 forward

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4 members · 3 offices
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DOCDB simple family 16903913
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Non-English titles
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›IP5 & PCT — 4 members
OfficePublicationKindPublishedFiledStatusTitle
USthis patentUS-5122847-AA16 Jun 19927 Sep 1988grantedNon-volatile semiconductor memory with CVD tunnel oxide
EPEP-0219241-A2A222 Apr 198723 Sep 1986publishedNichtflüchtiger Halbleiterspeicherde
EPEP-0219241-A3A324 Aug 198823 Sep 1986publishedNon-volatile semiconductor memory
JPJP-S6289364-AA23 Apr 198716 Oct 1985published不揮発性半導体記憶装置ja

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