Apparatus and method for data induced condition signaling

A method of controlling a processor in a digital data processing system as it is processing instructions in an instruction stream, comprising the steps of: generating, during processing of an instruction in said instruction stream, a condition flag indicating whether a fault condition exists and storing said condition flag in a predetermined location in said processor; executing, following generation of said condition flag, a fault instruction which tests the condition of said condition flag and executes a fault instruction sequence in response to said condition flag indicating a fault condition, and otherwise executing the next instruction in said instruction stream in response to another condition of said condition flag.

A digital data processor for processing instructions in an instruction stream, instructions comprising said instruction stream including a condition instruction type and a fault instruction, said processor including: A. condition instruction execution means for generating, during processing of an instruction in said instruction stream of said condition instruction type, a condition flag indicating whether a fault condition exists and storing said condition flag in a predetermined location in said processor; B. fault instruction execution means responsive to a subsequent fault instruction for testing the condition of said condition flag and executing a fault instruction sequence in response to said condition flag indicating a fault condition, and otherwise enabling said processor to execute the next instruction in said instruction stream in response to another condition of said condition flag.

A method of controlling a processor in a digital data processing system as it is processing instructions in an instruction stream, comprising the steps of: A. generating, during processing of an instruction in said instruction stream, a condition flag indicating whether a fault condition exists and storing said condition flag in a predetermined location in said processor; B. executing, following generation of said condition flag, a fault instruction which tests the condition of said condition flag, and: i. in response to said condition flag indicating a fault condition: a. storing a fault frame on a stack for use in identifying the condition including the steps of: I. storing an address pointing to said instruction on said stack; II. storing a processor status identification on said stack; and III. storing an address of an instruction which conditioned the condition flag on said stack; and b. executes a fault instruction sequence; ii. and otherwise executes the next instruction in said instruction stream in response to another condition of said condition flag.

A digital data processor for processing instructions in an instruction stream, instructions comprising said instruction stream including a condition instruction type and a fault instruction, said processor including: A. a plurality of registers B. condition instruction execution means for generating, during processing of an instruction in said instruction stream of said condition instruction type, conditioning a predetermined bit in a predetermined one of said registers to thereby indicating whether a fault condition exists; C. fault instruction execution means responsive to a subsequent fault instruction which tests the condition of said condition flag, including: i. fault condition means for testing said predetermined bit in said predetermined register to determine whether a fault condition exists, said fault condition means being responsive to said condition flag indicating a fault condition including: a. stack store means for storing a fault frame on a stack for use in identifying the condition including: I. means for storing an address pointing to said instruction on said stack; II. means for storing a processor status identification on said stack; and III. means for storing an address of an instruction which conditioned the condition flag on said stack; and b. means for executing a fault instruction sequence after said stack store means has stored said fault frame on said stack; and ii. next instruction execution means for executing the next instruction in said instruction stream in response to another condition of said condition flag.

A method of controlling a processor in a digital data processing system as it is processing instructions in an instruction stream, comprising the steps of: generating, during processing of an instruction in said instruction stream referencing an address, a condition flag indicating whether the referenced address is outside a predetermined range and that therefore a fault condition exists, and storing said condition flag in a predetermined location in said processor; executing, following generation of said condition flag, a fault instruction which tests the condition of said condition flag and executes a fault instruction sequence in response to said condition flag indicating a fault condition, and otherwise executing the next instruction in said instruction stream in response to another condition of said condition flag.

A digital data processor for processing instructions in an instruction stream, instructions comprising said instruction stream, said processor including: A. condition instruction execution means for generating, during processing of an instruction in said instruction stream referencing an address, a condition flag indicating whether the referenced address is outside a predetermined range, a condition flag indicating whether a fault condition exists and storing said condition flag in a predetermined location in said processor; B. fault instruction execution means responsive to a subsequent fault instruction for testing the condition of said condition flag and executing a fault instruction sequence in response to said condition flag indicating a fault condition, and otherwise enabling said processor to execute the next instruction in said instruction stream in response to another condition of said condition flag.

A method of controlling a processor in a digital data processing system as it is processing instructions in an instruction stream, comprising the steps of: A. generating, during processing of an instruction in said instruction stream referencing an address, a condition flag indicating whether the referenced address is outside a predetermined range and that therefore a fault condition exists, and storing said condition flag in a predetermined location in said processor; B. executing, following generation of said condition flag, a fault instruction which tests the condition of said condition flag, and: i. in response to said condition flag indicating a fault condition: a. storing a fault frame on a stack for use in identifying the condition including the steps of: I. storing an address pointing to said instruction on said stack; II. storing a processor status identification on said stack; and III. storing an address of an instruction which conditioned the condition flag on said stack; and b. executes a fault instruction sequence; ii. and otherwise executes the next instruction in said instruction stream in response to another condition of said condition flag.

A digital data processor for processing instructions in an instruction stream, instructions comprising said instruction stream including a condition instruction type and a fault instruction, said processor including: A. a plurality of registers B. condition instruction execution means for generating, during processing of an instruction in said instruction stream referencing an address, a condition flag indicating whether the referenced address is outside a predetermined range, a condition flag indicating whether a fault condition exists and storing said condition flag in a predetermined location in said processor; C. fault instruction execution means responsive to a subsequent fault instruction which tests the condition of said condition flag, including: i. fault condition means for testing said predetermined bit in said predetermined register to determine whether a fault condition exists, said fault condition means being responsive to said condition flag indicating a fault condition including: a. stack store means for storing a fault frame on a stack for use in identifying the condition including: I. means for storing an address pointing to said instruction on said stack; II. means for storing a processor status identification on said stack; and III. means for storing an address of an instruction which conditioned the condition flag on said stack; and b. means for executing a fault instruction sequence after said stack store means has stored said fault frame on said stack; and ii. next instruction execution means for executing the next instruction in said instruction stream in response to another condition of said condition flag.