Multi slice level signal circuit

An example of a conventional signal read out circuit included in a magnetic recording device is described in U.S. Pat. No. 4,081,756 (granted to Robert Price et al.). FIG. 1 shows the circuit construction of the above example. The operation of the example will be explained below, with reference to a timing chart shown in FIG. 2. Referring to FIGS. 1 and 2, a reproduced waveform 1 from a magnetic head is applied to a gate generator 8, which produces gate pulses from a reproduced waveform 1 by using a slice level 9, to obtain peak pulses corresponding to peak positions of the reproduced waveform. The peak pulses are applied to a detector 4, which produces read data synchronized with the output signal of a VFO (variable frequency oscillator) and sends the read data to an upper control device. In the above signal read out circuit, however, there arises a problem that when the reproduced waveform 1 has a waveform distortion which is indicated by a broken line in FIG. 2, on the basis of a defect in a recording medium or noise, an erroneous gate pulse is generated, and thus the read data contains an error. When the slice level is raised so as not to generate a gate pulse at a signal portion having the waveform distortion, it is impossible to generate a gate pulse at an undistorted signal portion having a low signal level and thus an error is produced in the read data. As mentioned above, according to the prior art, it is impossible to discriminate between a signal portion and noise which are equal in absolute value of amplitude level to each other.

An object of the present invention is to provide a signal read out circuit which can accurately discriminate between a true signal portion and noise which are equal in absolute value of amplitude level to each other, to obtain correct read data.

In order to attain the above object, a signal read out circuit according to the present invention includes a level gate generator using a plurality of slice levels such as a high slice level and a low slice level for a reproduced waveform, to obtain a plurality of gate pulse signals corresponding to the slice levels, and a level decision circuit for judging whether or not a signal portion is a true signal portion, o the basis of the gate pulse signals.

By using the plural slice levels and the level decision circuit, the present invention can obtain correct read data from the reproduced waveform, though erroneous read data may be obtained by the prior art.

In an ordinary case, signal portions appearing before and after a signal portion which has a waveform distortion as indicated by a broken line in FIG. 2, have correct (or undistorted) waveform. When a reproduced waveform shown at the top of FIG. 2 is observed, the noise indicated by the broken line can be discriminated from adjacent undistorted signal portions on the basis of the difference in signal level. In the prior art, however, individual signal portions are successively checked without utilizing information on adjacent signal portions, and hence it is impossible to discriminate between an undistorted signal portion and noise which is apart from the undistorted signal portion and has the same amplitude level as the undistorted signal portion. Thus, an erroneous read out operation is performed. According to the present invention, a plurality of slice levels are used for comparing with a reproduced waveform. A signal portion of the reproduced waveform, and a signal portion of the reproduced waveform is checked on the basis of the polarity of the signal portion, a different signal portion spaced apart from the signal portion a distance of one bit and the amplitude level of each signal portion determined by the slice levels. That is, the amount of information is increased, and thus a correct read out operation can be performed. The present invention will be explained below in more detail, with reference to FIG. 2. According to the present invention, a signal portion having a positive or negative high amplitude level is judged to be true (or undistorted). Further, a signal portion having a positive or negative low amplitude level is judged to be true only when the signal portion and a different signal portion spaced apart from the signal portion a distance of one bit are opposite in polarity to each other. Now, let us check the waveform shown at the top of FIG. 2, in accordance with the above rule. The first signal portion (that is, the leftmost peak) has a negative high amplitude level, and hence is considered to be true. The second signal portion has a positive low amplitude level, and the third signal portion has a positive high amplitude level. Hence, the second signal portion is not considered to be true, but the third signal portion is considered to be true. The fourth signal portion has a negative low amplitude level, and the fifth signal portion has a positive low amplitude level. Hence, the fourth signal portion is considered to be true. Thus, correct read data can be extracted from the above waveform.

FIG. 1 is a block diagram showing a conventional signal read out circuit.

FIG. 2 is a timing chart for explaining the operation of the conventional signal read out circuit and the present invention.

FIG. 3 is a block diagram showing the fundamental construction of a signal read out circuit according to the present invention.

FIGS. 4 to 6 are circuit diagrams showing the detailed circuit construction of an embodiment of a signal read out circuit according to the present invention.

FIG. 7 is a timing chart for explaining the operation of the embodiment of FIGS. 4 to 6.

FIGS. 8 to 12 are circuit diagrams showing the detailed circuit construction of another embodiment of a signal read out circuit according to the present invention.

FIGS. 13 and 14 are timing charts for explaining the operation of the embodiment of FIGS. 8 to 12.

FIGS. 15 and 16 are circuit diagrams showing the detailed circuit construction of a further embodiment of a signal read out circuit according to the present invention.

FIG. 17 is a timing chart for explaining the operation of the embodiment of FIGS. 15 and 16.

FIG. 18 is a circuit diagram showing another arrangement of SR-flip flops of FIG. 5 and FIG. 15.

FIG. 3 shows the fundamental construction of a signal read out circuit according to the present invention. Referring to FIG. 3, a reproduced waveform 1 from the signal reproducing circuit of a magnetic recording device is applied to a level gate generator 2, which produces gate pulse signals from the reproduced waveform 1 by using two slice levels (namely, a high slice level 6 and a low slice level 7). The gate pulse signals are applied to a level decision circuit 3 to judge whether the signal portion is true or not. The output of the level decision circuit 3 is applied to a detector 4 to obtain read data 5 synchronized with the output of a VFO. A few embodiments of the above-mentioned signal read out circuit will be explained below in detail.

In the present embodiment, the level gate generator 2 has a circuit configuration shown in FIG. 4, the level decision circuit 3 has a circuit configuration shown in FIG. 5, and the detector 4 has a circuit configuration shown in FIG. 6. FIG. 7 is a timing chart showing various signals which are generated in the present embodiment. Now, the operation of the present embodiment will be explained, with reference to FIGS. 4 to 7.

The reproduced waveform 1 is differentiated by a differentiation circuit 10, and then applied to a limiter 11. Thus, a zero-cross signal which includes pulse signals Limit Pulse-P and Limit Pulse-N, is obtained. Further, four gate pulse signals High Gate P, Low Gate P, High Gate N and Low Gate N are produced by using the high slice level 6, the low slice level 7 and four limiters 12 to 15 for the reproduced waveform 1. The six signals thus obtained are applied to the level decision circuit shown in FIG. 5. In the level decision circuit, four pulse signals High Pulse P, High Pulse N, Low Pulse P and Low Pulse N signals, which are the zero-cross pulse signals extracted with the gate, are first produced from the six signals applied to the level decision circuit. The four pulse signals thus obtained are applied to a VFO circuit 16 and VFO detectors 17 to 20 as shown in FIG. 5, to obtain four signals HP n , HN n , LP n and LN n synchronized with a VFO signal (namely, the output of the VFO circuit 16). The signals HP n , HN n , LP n and LN n indicate the present state of the reproduced waveform 1. It is evident that the pulse signals Low Pulse P and Low Pulse N may be used as a source signal for driving the VFO circuit in synchronism therewith, in place of the pulse signals High Pulse P and High Pulse N that are shown in FIG. 5 as driving the VFO circuit. Further, in the level decision circuit, signals LP n-1 and LN n-1 corresponding to the previous state of the signals LP n and LN n are formed by flip-flops. Then, the signals HP n , HN n , LP n , LN n , LP n-1 and LN n-1 are applied to logical circuits as shown in FIG. 5, to obtain signals H n , H n +L n , Load R1 and Load R0 which are expressed by the following equations:

H.sub.n =HP.sub.n +HN.sub.n

H.sub.n +L.sub.n =HP.sub.n +HN.sub.n +LP.sub.n +LN.sub.n

Load R1=LP.sub.n-1 ·(HP.sub.n +LP.sub.n)+LN.sub.n-1 ·(HN.sub.n +LN.sub.n)

Load R0=LP.sub.n-1 ·(HN.sub.n +LN.sub.n)+LN.sub.n-1 ·(HP.sub.n +LP.sub.n)

The signal H n indicates bits, at which a signal amplitude level exceeds a positive or negative high slice level. The signal H n +L n indicates bits, at which an amplitude level exceeds at least a positive or negative low slice level, to indicate that the bits may be desired data. The signal Load R1 indicates that a bit just before a pulse of the signal has a logical value "0". The signal Load R0 indicates that a bit just before a pulse of the signal has a logical value "1".

These signals H n , H n +L n , Load R1 and Load R0 and a clock signal VFO clock-P from the VFO circuit 16 are applied to the detector of FIG. 6. Thus, correct read data is obtained in the following manner. The signal H n +L n indicating data which may be correct data, is applied to a shift register-1, and the signal H n indicating correct data is applied to a shift register-0. These input signals are shifted in accordance with the clock pulse VFO clock-P. The logical values inputted to the two shift registers may be different from each other at a time the reproduced waveform 1 exceeds only a positive or negative low slice level, since it is not known at this time whether an input bit is correct or not. It is judged whether the above bit is correct or not, after the next bit has been inputted. That is, the signal Load R1 or Load R0 is applied to the shift register-1 or shift register-0, and the contents of one of the two shift registers are loaded into the other shift register, to equalize the input contents to the two shift registers. Thus, the contents of one of the two shift registers coincide with the contents of the other shift register in a period when the input signals are shifted by n bits, and correct read data 5 is obtained. The operation of the detector of FIG. 6 will be explained below in more detail, with reference to FIG. 7. In a case where the reproduced waveform 1 contains noise as indicated by a broken line, a pulse corresponding to the noise is applied to the shift register-1, but is not applied to the shift register-0. At the next bit, the signal Load R1 is applied to the shift register-1, and thus it is known that the above pulse is not a correct one. Accordingly, a logical value inputted to the shift register-0 is loaded into the shift register-1, to correct the bit of the shift register-1 corresponding to the above pulse. Thereafter, the contents of each shift register are shifted by one bit, and then new data are applied to the two shift registers. Accordingly, at the first bit and bits following thereto, the shift register-1 and the shift register-0 have the same contents. Further, a correct signal portion exceeding only a positive or negative low slice level is opposite in polarity to a signal portion adjacent thereto. That is, a pulse corresponding to the above signal portion is judged to be correct, at the next bit. Thus, the signal Load R0 is applied to the shift register-0, and a logical value inputted to the shift register-1 is loaded into the shift register-0, to correct the contents of the shift register-0. Thereafter, the contents of each shift register are shifted by one bit.

As mentioned above, according to the present embodiment, correct read data can be obtained from the low-quality reproduced waveform shown at the top of FIG. 7, though it is impossible to obtain correct read data by the prior art.

The number of bits included in each of the shift register-1 and the shift register-0 is determined in accordance with a coding method used. In the 2 to 7 coding method or 1 to 7 coding method, each shift register includes nine bits or less. The read data from the detector 4 is decoded in a manner corresponding to the coding method.

In the present embodiment, two positive slice levels and two negative levels are used. Three or more positive slice levels and three or more negative slice levels may be used. In this case, three or more shift registers are used to improve the performance of a signal read out circuit. Further, the slice levels may be varied by an external control signal.

The present embodiment has the fundamental construction shown in FIG. 3. In the present embodiment, the level gate generator 2 has a circuit configuration shown in FIG. 4, the level decision circuit 3 has a circuit configuration shown in FIG. 8, and the detector 4 has a circuit configuration shown in FIG. 9. FIGS. 10 to 12 show examples of the reset generator 22, the set generator 23 and the delayed gate generator 28 of FIG. 8, respectively. FIGS. 13 and 14 are timing charts showing various signals which are generated in the present embodiment.

Now, the operation of the present embodiment will be explained, with reference to FIGS. 4 and 8 to 14.

The operation of the level gate generator 2 is the same as mentioned in the EMBODIMENT I, and hence the pulse signals Limit Pulse-P and Limit Pulse-N and the gate pulse signals High Gate P, High Gate N, Low Gate P and Low Gate N are delivered from the level gate generator 2. The six signals thus obtained are applied to the level decision circuit 3 shown in FIG. 8. The operation of the above level decision circuit is as follows. The six signals are delayed by a time τ d . In this delay time, a read gate pulse signal containing only correct read gate pulses is produced from the gate pulse signals. A read pulse signal, containing pulses which are the zero-cross pulse signals extracted as the correct read gate pulses, is produced from the read gate pulse signal, the pulse signals Limit Pulse-P and Limit Pulse-N, and other signals. Then, read data synchronized with the output of a VFO circuit 16 is produced from the read pulse signal by the detector 4.

In order to obtain the correct read gate pulses, a set signal including all pulses which may be correct ones, is formed by a set generator 23, and all the pulses included in the set signal are successively allotted to delayed gate generators 28 with the aid of a counter 24 and a decoder 27. While, a reset signal including only erroneous ones of the above pulses is formed by a reset generator 22, to be applied to the delayed gate generators 28 in a state that the reset signal is shifted in relation to the set signal by one bit, with the aid of the counter 24 and another decoder 26. Thus, the set signals of delayed gate generators applied with the erroneous pulses are reset. FIG. 14 shows the operation of delayed gate generators in detail.

As mentioned above, according to the present embodiment, only correct read gate pulses are obtained, to produce correct read pulses, and correct read data can be obtained from the correct read pulses.

Although the circuit configurations of the reset generator 22, the set generator 23 and the delayed gate generator 28 are shown in FIGS. 10, 11 and 12, respectively, these generators 22, 23 and 28 may have other circuit configurations than those shown in FIGS. 10 to 12, provided that other circuit configurations perform the same operations as made by the circuit configurations of FIGS. 10 to 12.

Further, not only the number n of bits included in each of the counter 24, the decoders 26 and 27, and the delayed gate generator 28, but also the delay time τ d is determined in accordance with a coding method used. However, when a maximum time interval between adjacent bits and a minimum time interval between adjacent bits are expressed by T max and T min , respectively, it is desirable to satisfy a relation T MAX <τ d <n×T min .

Similarly to the embodiment described in the EMBODIMENT I, in the present embodiment, also, three or more positive slice levels and three or more negative slice levels may be used, and further slice levels may be varied by an external control signal.

The present embodiment has the fundamental construction shown in FIG. 3. In the present embodiment, the level gate generator 2 has a circuit configuration shown in FIG. 4, the level decision circuit 3 has a circuit configuration shown in FIG. 15, and the detector 4 has a circuit configuration shown in FIG. 16. FIG. 17 is a timing chart for explaining the operation of the level decision circuit of FIG. 15.

The operation of the present embodiment will be explained below. The operation of the level gate generator 2 is the same as mentioned in the EMBODIMNET I, and hence the pulse signals Limit Pulse-P and Limit Pulse-N and the gate pulse signals High Gate P, High Gate N, Low Gate P and Low Gate N are delivered from the level gate generator 2. These signals are applied to the level decision circuit shown in FIG. 15, to form Raw Data including all of pulses corresponding to gate pulses, and an inhibit pulse signal Inhibit indicating that a pulse just prior to an inhibit pulse is erroneous.

The Raw Data is formed in the following manner. As in the EMBODIMENT I, the pulse signals High Pulse P, High Pulse N, Low Pulse P and Low Pulse N which are the zero-cross pulse signals extracted with the gate pulse signals, are first produced. Then, a high pulse signal High Pulse is produced by applying the pulse signals High Pulse P and High Pulse N to an OR circuit, and a low pulse signal Low Pulse is produced by applying the pulse signals Low Pulse P and Low Pulse N to another OR circuit. The signals High Pulse and Low Pulse are shaped so that pulses contained therein have an appropriate pulse width, and then applied to an OR circuit, to obtain the Raw Data. The inhibit pulse is generated when a pulse of the low pulse signal is followed by a pulse of the high pulse signal which is equal in polarity to the pulse of the low pulse signal. In more detail, a delayed low pulse signal Delay Low Pulse obtained by delaying the low pulse signal Low Pulse, the high pulse signal High Pulse and a D-type flip-flop are used as shown in FIG. 15, to generate the inhibit pulse.

The Raw Data and the inhibit signal thus obtained are applied to the detector shown in FIG. 16, to synchronize the Raw Data and the inhibit signal with a VFO clock by using a VFO circuit 16, a VFO detector 17 and a D-type flip-flop. The Raw Data synchronized with the VFO clock is shifted in a shift register made up of flip-flops. When the inhibit pulse is applied to the shift register in a period, during which the Raw Data is shifted in the shift register, the logical value "1" at a bit just prior to the inhibit pulse is erased by the circuit configuration of FIG. 16. Thus, the shift register transmits the Raw Data while eliminating an erroneous pulse from the Raw Data.

As mentioned above, according to the present embodiment, only an erroneous pulse is eliminated from pulses which may produce a logical value "1", and thus correct read data can be obtained.

Although the level decision circuit 3 and the detector 4 of the present embodiment have circuit configurations shown in FIGS. 15 and 16, the level decision circuit 3 and the detector 4 may have other circuit configurations than those shown in FIGS. 15 and 16, provided that other circuit configurations can produce the Raw Data, the inhibit signal and the correct read data. Further, the arrangement of SR-flip-flops in FIG. 15 may be replaced by the arrangement shown in FIG. 18. As is evident from the above, various changes and modifications can be made in the circuit configuration of the present embodiment, without losing the advantage of the present invention. It is needless to say that various changes and modifications can also be made in the circuit configurations described in the EMBODIMENTS I and II.

Similarly to the embodiments described in the EMBODIMENTS I and II, three or more positive slice levels and three or more negative slice levels can be used in the present embodiment. Further, the slice levels used in the present embodiment may be varied by a control signal.

Similarly to the shift register-1 and shift register-0 shown in FIG. 6, the number of stages of the shift register shown in FIG. 16 is determined in accordance with a coding method used.

As has been explained in the forgoing, according to the present invention, correct read data can be obtained from a low-quality, reproduced waveform which has a waveform distortion and is low in signal-to-noise ratio, though it is impossible to obtain the correct read data by the prior art. In more detail, according to the present invention, it is possible to discriminate between a signal portion and noise having the same amplitude level, and only true signal portions are extracted from the reproduced waveform. Thus, a magnetic recording device can be obtained which is high in reliability and excellent in performance.