Semiconductor memory device and method of fabricating the same

Korean Patent Application No. 10-2020-0132761, filed on Oct. 14, 2020, in the Korean Intellectual Property Office, and entitled: “Semiconductor Memory Device and Method of Fabricating the Same,” is incorporated by reference herein in its entirety.

1. Field

Embodiments relate to a semiconductor memory device and a method of fabricating the same

2. Description of the Related Art

As semiconductor memory devices increasingly become highly integrated, high-performance memory devices operating fast at low operating voltages have been considered. Recently, variable resistance memory devices having variable resistance characteristics have been considered. For example, phase-change random access memory (PRAM) devices, magnetic random access memory (MRAM) devices, and resistive random access memory (RRAM) devices have been considered as variable resistance memory devices.

The embodiments may be realized by providing a semiconductor memory device including a first lower conductive line and a second lower conductive line each extending in a first direction and being spaced apart from each other in a second direction intersecting the first direction; a first middle conductive line on the first lower conductive line and the second lower conductive line and extending in the second direction; a first memory cell between the first lower conductive line and the first middle conductive line; a second memory cell between the second lower conductive line and the first middle conductive line; an air gap support layer between the first memory cell and the second memory cell; and a first air gap between the first memory cell and the second memory cell and under the air gap support layer, wherein an upper surface of the air gap support layer lies in a same plane as an upper surface of the first memory cell and an upper surface of the second memory cell, the first memory cell includes a first ovonic threshold switching (OTS) layer and a first phase-change layer, the second memory cell includes a second OTS layer and a second phase-change layer, and the first air gap overlaps the first phase-change layer and the second phase-change layer in the second direction.

The embodiments may be realized by providing a semiconductor memory device including a first lower conductive line and a second lower conductive line each extending in a first direction and being spaced apart from each other in a second direction intersecting the first direction; a first middle conductive line and a second middle conductive line on the first lower conductive line and the second lower conductive line, the first middle conductive line and the second middle conductive line each extending in the second direction and being spaced apart from each other in the first direction; a first memory cell between the first lower conductive line and the first middle conductive line; a second memory cell between the second lower conductive line and the first middle conductive line; a first air gap support layer between the first memory cell and the second memory cell; a first air gap between the first memory cell and the second memory cell and under the first air gap support layer; a second air gap between the first lower conductive line and the second lower conductive line; and a third air gap between the first middle conductive line and the second middle conductive line, wherein an upper surface of the first air gap support layer lies in a same plane as an upper surface of the first memory cell and an upper surface of the second memory cell, the first memory cell includes a first ovonic threshold switching (OTS) layer and a first phase-change layer, the second memory cell includes a second OTS layer and a second phase-change layer, and the first air gap overlaps the first and second phase-change layers in the second direction.

The embodiments may be realized by providing a method of fabricating a semiconductor memory device, the method including forming a first lower conductive line and a second lower conductive line extending in a first direction and being spaced apart from each other in a second direction intersecting the first direction; forming a first memory cell on the first lower conductive line; forming a second memory cell on the second lower conductive line; forming an insulating layer along profiles of the first memory cell and the second memory cell; forming a mold carbon layer on the insulating layer; forming an air gap support layer on the mold carbon layer; forming an air gap by removing the mold carbon layer by performing a heat treatment process; and forming a first middle conductive line and a second middle conductive line, which extend in the second direction and are spaced apart from each other in the first direction, on the first memory cell and the second memory cell, wherein the first memory cell includes a first ovonic threshold switching (OTS) layer and a first phase-change layer, the second memory cell includes a second OTS layer and a second phase-change layer, and the air gap is formed between the first memory cell and the second memory cell and overlaps the first phase-change layer and the second phase-change layer in the second direction.

Features will be apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which:

FIG. 1 is a layout view of a semiconductor memory device according to embodiments of the present disclosure.

FIGS. 2 A through 2 C are cross-sectional views taken along line A-A of FIG. 1 .

FIGS. 3 A through 3 C are cross-sectional views taken along line B-B of FIG. 1 .

FIGS. 4 through 11 are views of stages in a method of fabricating a semiconductor memory device according to embodiments of the present disclosure.

FIGS. 12 through 20 are views of stages in a method of fabricating a semiconductor memory device according to the embodiments of the present disclosure.

FIGS. 21 through 30 are views of stages in a method of fabricating a semiconductor memory device according to the embodiments of the present disclosure.

FIGS. 31 through 39 are views of stages in a method of fabricating a semiconductor memory device according to the embodiments of the present disclosure.

A semiconductor memory device according to embodiments of the present disclosure will now be described with reference to FIGS. 1 through 3 C .

FIG. 1 is a layout view of a semiconductor memory device according to embodiments of the present disclosure. FIGS. 2 A through 2 C are cross-sectional views taken along line A-A of FIG. 1 . FIGS. 3 A through 3 C are cross-sectional views taken along line B-B of FIG. 1 .

Referring to FIGS. 1 through 3 C , the semiconductor memory device according to the embodiments may include a substrate 100 , a first lower conductive line WL 1 , a second lower conductive line WL 2 , a first middle conductive line BL 1 , a second middle conductive line BL 2 , a first upper conductive line WL 3 , a second upper conductive line WL 4 , and first through sixth memory cells MC 1 through MC 6 .

The substrate 100 may be a semiconductor substrate. In an implementation, the substrate 100 may be bulk silicon or silicon-on-insulator (SOI). In an implementation, the substrate 100 may be a silicon substrate or a substrate made of another material such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate 100 may consist of a base substrate and an epitaxial layer formed on the base substrate. As used herein, the term “or” is not an exclusive term, e.g., “A or B” would include A, B, or A and B.

The first and second lower conductive lines WL 1 and WL 2 may be on the substrate 100 . The first lower conductive line WL 1 may extend (e.g., lengthwise) in a first direction X. The second lower conductive line WL 2 may extend (e.g., lengthwise) in the first direction X and may be spaced apart from the first lower conductive line WL 1 in a second direction Y. The first direction X and the second direction Y may intersect each other. In an implementation, the first direction X and the second direction Y may be perpendicular to each other.

The first and second middle conductive lines BL 1 and BL 2 may be on the first and second lower conductive lines WL 1 and WL 2 and spaced part from the first and second lower conductive lines WL 1 and WL 2 in a third direction Z. The third direction Z may intersect the first direction X and the second direction Y. In an implementation, the third direction Z may be perpendicular to the first direction X and the second direction Y.

The first middle conductive line BL 1 may extend (e.g., lengthwise) in the second direction Y. The second middle conductive line BL 2 may extend (e.g., lengthwise) in the second direction Y and may be spaced apart from the first middle conductive line BL 1 in the first direction X.

The first upper conductive line WL 3 may be on the first and second middle conductive lines BL 1 and BL 2 and spaced apart from the first and second middle conductive lines BL 1 and BL 2 in the third direction Z. The first upper conductive line WL 3 may extend (e.g., lengthwise) in the first direction X. The second upper conductive line WL 4 may extend (e.g., lengthwise) in the first direction X and may be spaced apart from the first upper conductive line WL 3 in the second direction Y.

The first upper conductive line WL 3 and the first lower conductive line WL 1 may overlap in the third direction Z. The second upper conductive line WL 4 and the second lower conductive line WL 2 may overlap in the third direction Z.

The first upper conductive line WL 3 and the first lower conductive line WL 1 may completely overlap in the third direction Z. The second upper conductive line WL 4 and the second lower conductive line WL 2 may completely overlap in the third direction Z.

Each of the first and second lower conductive lines WL 1 and WL 2 , the first and second middle conductive lines BL 1 and BL 2 , and the first and second upper conductive lines WL 3 and WL 4 may include, e.g., tungsten (W), tungsten nitride (WN gold (Au), silver (Ag), copper (Cu) aluminum (Al), titanium aluminum nitride (TiAlN), nickel (Ni), cobalt (Co), chromium (Cr), tin (Sn), zinc (Zn), indium tin oxide (ITO), or combinations of the same.

The first and second lower conductive lines WL 1 and WL 2 , the first and second middle conductive lines BL 1 and BL 2 , and the first and second upper conductive lines WL 3 and WL 4 may include the same material or may include different materials.

In an implementation, each of the first and second lower conductive lines WL 1 and WL 2 , the first and second middle conductive lines BL 1 and BL 2 , and the first and second upper conductive lines WL 3 and WL 4 may include tungsten (W).

In an implementation, the first and second lower conductive lines WL 1 and WL 2 and the first and second upper conductive lines WL 3 and WL 4 may be word lines, and the first and second middle conductive lines BL 1 and BL 2 may be bit lines.

Interlayer insulating films 105 , 205 , and 305 may be on the substrate 100 . The interlayer insulating film 105 may electrically insulate the first and second lower conductive lines WL 1 and WL 2 . The interlayer insulating film 205 may electrically insulate the first and second middle conductive lines BL 1 and BL 2 . The interlayer insulating film 305 may electrically insulate the first and second upper conductive lines WL 3 and WL 4 . The interlayer insulating films 105 , 205 and 305 may include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or combinations of the same.

The memory cells MC 1 through MC 6 may be on the substrate 100 . The first memory cell MC 1 may be at an intersection of the first lower conductive line WL 1 and the first middle conductive line BL 1 . The first memory cell MC 1 may be between the first lower conductive line WL 1 and the first middle conductive line BL 1 .

The second memory cell MC 2 may be at an intersection of the second lower conductive line WL 2 and the first middle conductive line BL 1 . The second memory cell MC 2 may be between the second lower conductive line WL 2 and the first middle conductive line BL 1 .

The third memory cell MC 3 may be at an intersection of the first lower conductive line WL 1 and the second middle conductive line BL 2 . The third memory cell MC 3 may be between the first lower conductive line WL 1 and the second middle conductive line BL 2 .

The fourth memory cell MC 4 may be at an intersection of the first upper conductive line WL 3 and the first middle conductive line BL 1 . The fourth memory cell MC 4 may be between the first upper conductive line WL 3 and the first middle conductive line BL 1 .

The fifth memory cell MC 5 may be at an intersection of the second upper conductive line WL 4 and the first middle conductive line BL 1 . The fifth memory cell MC 5 may be between the second upper conductive line WL 4 and the first middle conductive line BL 1 .

The sixth memory cell MC 6 may be at an intersection of the first upper conductive line WL 3 and the second middle conductive line BL 2 . The sixth memory cell MC 6 may be between the first upper conductive line WL 3 and the second middle conductive line BL 2 .

The first and second memory cells MC 1 and MC 2 may electrically connect the first and second lower conductive lines WL 1 and WL 2 to the first middle conductive line BL 1 , respectively.

The third memory cell MC 3 may electrically connect the first lower conductive line WL 1 and the second middle conductive line BL 2 .

The fourth and fifth memory cells MC 4 and MC 5 may electrically connect the first and second upper conductive lines WL 3 and WL 4 to the first middle conductive line BL 1 , respectively.

The sixth memory cell MC 6 may electrically connect the first upper conductive line WL 3 and the second middle conductive line BL 2 .

The first memory cell MC 1 may be overlapped by the fourth memory cell MC 4 in the third direction Z. The second memory cell MC 2 may be overlapped by the fifth memory cell MC 5 in the third direction Z. The third memory cell MC 3 may be overlapped by the sixth memory cell MC 6 in the third direction Z.

The first through sixth memory cells MC 1 through MC 6 may include first through sixth lower electrodes 110 , 210 , 310 , 410 , 510 and 610 , respectively. The first through third lower electrodes 110 , 210 and 310 may be on the first and second lower conductive lines WL 1 and WL 2 . The fourth through sixth lower electrodes 410 , 510 and 610 may be on the first and second middle conductive lines BL 1 and BL 2 .

The first and third lower electrodes 110 and 310 may be electrically connected to the first lower conductive line WL 1 by contacting (e.g., directly contacting) the first lower conductive line WL 1 . Each of the fourth and fifth lower electrodes 410 and 510 may be electrically connected to the first middle conductive line BL 1 by contacting (e.g., directly contacting) the first middle conductive line BL 1 . The second lower electrode 210 may be electrically connected to the second lower conductive line WL 2 by contacting (e.g., directly contacting) the second lower conductive line WL 2 . The sixth lower electrode 610 may be electrically connected to the second middle conductive line BL 2 by contacting (e.g., directly contacting) the second middle conductive line BL 2 .

The first through sixth memory cells MC 1 through MC 6 may include first through sixth middle electrodes 130 , 230 , 330 , 430 , 530 and 630 , respectively. The first through sixth middle electrodes 130 , 230 , 330 , 430 , 530 and 630 may be on the first through sixth lower electrodes 110 , 210 , 310 , 410 , 510 and 610 , respectively.

The first through sixth memory cells MC 1 through MC 6 may include first through sixth upper electrodes 150 , 250 , 350 , 450 , 550 and 650 , respectively. The first through sixth upper electrodes 150 , 250 , 350 , 450 , 550 and 650 may be on the first through sixth middle electrodes 130 , 230 , 330 , 430 , 530 and 630 , respectively.

The first and second upper electrodes 150 and 250 may be electrically connected to the first middle conductive line BL 1 by contacting (e.g., directly contacting) the first middle conductive line BL 1 . The third upper electrode 350 may be electrically connected to the second middle conductive line BL 2 by contacting (e.g., directly contacting) the second middle conductive line BL 2 . The fourth and sixth upper electrodes 450 and 650 may be electrically connected to the first upper conductive line WL 3 by contacting (e.g., directly contacting) the first upper conductive line WL 3 . The fifth upper electrode 550 may be electrically connected to the second upper conductive line WL 4 by contacting (e.g., directly contacting) the second upper conductive line WL 4 .

Each of the first through sixth lower electrodes 110 , 210 , 310 , 410 , 510 and 610 , the first through sixth middle electrodes 130 , 230 , 330 , 430 , 530 and 630 , and the first through sixth upper electrodes 150 , 250 , 350 , 450 , 550 and 650 may include a metal or a metal nitride, e.g., tungsten (W), platinum (Pt), palladium (Pd), rhodium (Rh), ruthenium (Ru), iridium (Ir), copper (Cu), aluminum (Al), titanium (Ti) or tantalum (Ta), titanium nitride (TiN), or a combination of the same. In an implementation, the first through sixth lower electrodes 110 , 210 , 310 , 410 , 510 and 610 , the first through sixth middle electrodes 130 , 230 , 330 , 430 , 530 and 630 , and the first through sixth upper electrodes 150 , 250 , 350 , 450 , 550 and 650 may include a carbon (C) layer.

The first through sixth memory cells MC 1 through MC 6 may include first through sixth ovonic threshold switching (OTS) layers 120 , 220 , 320 , 420 , 520 and 620 , respectively.

In an implementation, the first through sixth OTS layers 120 , 220 , 320 , 420 , 520 and 620 may be between the first through sixth lower electrodes 110 , 210 , 310 , 410 , 510 and 610 and the first through sixth middle electrodes 130 , 230 , 330 , 430 , 530 and 630 , respectively.

The first through sixth OTS layers 120 , 220 , 320 , 420 , 520 and 620 may help control current flows in the first through sixth memory cells MC 1 through MC 6 , respectively.

In an implementation, the first through sixth OTS layers 120 , 220 , 320 , 420 , 520 and 620 may have OTS characteristics. In an implementation, when the first through sixth OTS layers 120 , 220 , 320 , 420 , 520 and 620 are in an OFF state (high resistance state), if a voltage equal to or higher than a specific voltage (threshold switching voltage) is applied to the first through sixth OTS layers 120 , 220 , 320 , 420 , 520 and 620 , the first through sixth OTS layers 120 , 220 , 320 , 420 , 520 and 620 may be changed to an ON state (low resistance state).

In an implementation, when the first through sixth OTS layers 120 , 220 , 320 , 420 , 520 and 620 are in the ON state (low resistance state), if the voltage applied to the first through sixth OTS layers 120 , 220 , 320 , 420 , 520 and 620 is lowered to a specific voltage (sustain voltage) or less, the first through sixth OTS layers 120 , 220 , 320 , 420 , 520 and 620 may be restored to the OFF state (high resistance state).

The first through sixth OTS layers 120 , 220 , 320 , 420 , 520 and 620 may include, e.g., a chalcogenide material. The chalcogenide material may include a compound including a combination of S, The, or Se, which are chalcogen elements, and Ge, Sb, Bi, Al, Tl, Sn, Zn, As, Si, In, Ti, Ga, or P.

In an implementation, the first through sixth OTS layers 120 , 220 , 320 , 420 , 520 and 620 may include, e.g., GeSe, GeS, AsSe, AsTe, AsS, SiTe, SiSe, SiS, GeAs, SiAs, SnSe, SnTe, GeAsTe, GeAsSe, AlAsTe, AlAsSe, SiAsSe, SiAsTe, GeSeTe, GeSeSb, GaAsSe, GaAsTe, InAsSe, InAsTe, SnAsSe, SnAsTe, GeSiAsTe, GeSiAsSe, GeSiSeTe, GeSeTeSb, GeSiSeSb, GeSiTeSb, GeSeTeBi, GeSiSeBi, GeSiTeBi, GeAsSeSb, GeAsTeSb, GeAsTeBi, GeAsSeBi, GeAsSeIn, GeAsSeGa, GeAsSeAl, GeAsSeTl, GeAsSeSn, GeAsSeZn, GeAsTeIn, GeAsTeGa, GeAsTeAl, GeAsTeTl, GeAsTeSn, GeAsTeZn, GeSiAsSeTe, GeAsSeTeS, GeSiAsSeS, GeSiAsTeS, GeSiSeTeS, GeSiAsSeP, GeSiAsTeP, GeAsSeTeP, GeSiAsSeIn, GeSiAsSeGa, GeSiAsSeAl, GeSiAsSeTl, GeSiAsSeZn, GeSiAsSeSn, GeSiAsTeIn, GeSiAsTeGa, GeSiAsTeAl, GeSiAsTeTl, GeSiAsTeZn, GeSiAsTeSn, GeAsSeTeIn, GeAsSeTeGa, GeAsSeTeAl, GeAsSeTeTl, GeAsSeTeZn, GeAsSeTeSn, GeAsSeSIn, GeAsSeSGa, GeAsSeSAl, GeAsSeSTl, GeAsSeSZn, GeAsSeSSn, GeAsTeSIn, GeAsTeSGa, GeAsTeSAl, GeAsTeSTl, GeAsTeSZn, GeAsTeSSn, GeAsSeInGa, GeAsSeInAl, GeAsSeInTl, GeAsSeInZn, GeAsSeInSn, GeAsSeGaAl, GeAsSeGaTl, GeAsSeGaZn, GeAsSeGaSn, GeAsSeAlTl, GeAsSeAlZn, GeAsSEAlSn, GeAsSeTlZn, GeAsSeTlSn, GeAsSeZnSn, GeSiAsSeTeS, GeSiAsSeTeIn, GeSiAsSeTeGa, GeSiAsSeTeAl, GeSiAsSeTeTl, GeSiAsSeTeZn, GeSiAsSeTeSn, GeSiAsSeTeP, GeSiAsSeSIn, GeSiAsSeSGa, GeSiAsSeSAl, GeSiAsSeSTl, GeSiAsSeSZn, GeSiAsSeSSn, GeAsSeTeSIn, GeAsSeTeSGa, GeAsSeTeSAl, GeAsSeTeSTl, GeAsSeTeSZn, GeAsSeTeSSn, GeAsSeTePIn, GeAsSeTePGa, GeAsSeTePAl, GeAsSeTePTl, GeAsSeTePZn, GeAsSeTePSn, GeSiAsSeInGa, GeSiAsSeInAl, GeSiAsSeInTl, GeSiAsSeInZn, GeSiAsSeInSn, GeSiAsSeGaAl, GeSiAsSeGaTl, GeSiAsSeGaZn, GeSiAsSeGaSn, GeSiAsSeAlSn, GeAsSeTeInGa, GeAsSeTeInAl, GeAsSeTeInTl, GeAsSeTeInZn, GeAsSeTeInSn, GeAsSeTeGaAl, GeAsSeTeGaTl, GeAsSeTeGaZn, GeAsSeTeGaSn, GeAsSeTeAlSn, GeAsSeSInGa, GeAsSeSInAl, GeAsSeSInTl, GeAsSeSInZn, GeAsSeSInSn, GeAsSeSGaAl, GeAsSeSGaTl, GeAsSeSGaZn, GeAsSeSGaSn, or GeAsSeSAlSn.

The first through sixth memory cells MC 1 through MC 6 may include the first through sixth phase-change layers 140 , 240 , 340 , 440 , 540 and 640 , respectively.

In an implementation, the first through sixth phase-change layers 140 , 240 , 340 , 440 , 540 and 640 may be between the first through sixth middle electrodes 130 , 230 , 330 , 430 , 530 and 630 and the first through sixth upper electrodes 150 , 250 , 350 , 450 , 550 and 650 , respectively. In an implementation, the first through sixth phase-change layers 140 , 240 , 340 , 440 , 540 and 640 may swap places with the first through sixth OTS layers 120 , 220 , 320 , 420 , 520 and 620 , respectively.

The first through sixth phase-change layers 140 , 240 , 340 , 440 , 540 and 640 may electrically connect the first through sixth middle electrodes 130 , 230 , 330 , 430 , 530 and 630 and the first through sixth upper electrodes 150 , 250 , 350 , 450 , 550 and 650 , respectively. The first through sixth phase-change layers 140 , 240 , 340 , 440 , 540 and 640 may be phase-change patterns. In an implementation, the first through sixth phase-change layers 140 , 240 , 340 , 440 , 540 and 640 may store data by changing their resistance according to a temperature change.

The first through sixth phase-change layers 140 , 240 , 340 , 440 , 540 and 640 may include a compound including a combination of, e.g., S, Te, or Se, which are chalcogen elements, and Ge, Sb, Bi, Sn, Ag, As, Si, In, Ga, Ce, Y, Al, Tl, Nd, Dy, Sc, or Zn.

In an implementation, the first through sixth phase-change layers 140 , 240 , 340 , 440 , 540 and 640 may include, e.g., GeTe, GeSe, GeS, SbSe, SbTe, SbS, SbSe, SnSb, InSe, InSb, AsTe, AlTe, GaSb, AlSb, BiSb, ScSb, YSb, CeSb, DySb, NdSb, GeSbSe, AlSbTe, AlSbSe, SiSbSe, SiSbTe, GeSeTe, InGeTe, GeSbTe, GeAsTe, SnSeTe, GeGaSe, BiSbSe, GaSeTe, InGeSb, GaSbSe, GaSbTe, InSbSe, InSbTe, SnSbSe, SnSbTem ScSbTe, ScSbSe, ScSbS, TSbTe, TSbSe, TSbS, CeSbTe, CeSbSe, CeSbS, DySbTe, DySbSe, DySbS, NdSbTe, NdSbSe, NdSbS, GeSbTeS, BiSbTeSe, AgInSbTe, GeSbSeTe, GeSnSbTe, SiGeSbTe, SiGeSbSe, SiGeSeTe, BiGeSeTe, BiSiGeSe, BiSiGeTe, GeSbTeBi, GeSbSeBi, GeSbSeIn, GeSbSeGa, GeSbSeAl, GeSbSeTl, GeSbSeSn, GeSbSeZn, GeSbTeIn, GeSbTeGa, GeSbTeAl, GeSbTeTl, GeSbTeSn, GeSbTeZn, ScGeSbTe, ScGeSbSe, ScGeSbS, YGeSbTe, YGeSbSe, YGeSbS, CeGeSbTe, CeGeSbSe, CeGeSbS, DyGeSbTe, DyGeSbSe, DyGeSbS, NdGeSbTe, NdGeSbSe, NdGeSbS, InSbTeAsSe, GeScSbSeTe, GeSbSeTeS, GeScSbSeS, GeScSbTeS, GeScSeTeS, GeScSbSeP, GeScSbTeP, GeSbSeTeP, GeScSbSeIn, GeScSbSeGa, GeScSbSeAl, GeScSbSeTl, GeScSbSeZn, GeScSbSeSn, GeScSbTeIn, GeScSbTeGa, GeSbAsTeAl, GeScSbTeTl, GeScSbTeZn, GeScSbTeSn, GeSbSeTeIn, GeSbSeTeGa, GeSbSeTeAl, GeSbSeTeTl, GeSbSeTeZn, GeSbSeTeSn, GeSbSeSIn, GeSbSeSGa, GeSbSeSAl, GeSbSeSTl, GeSbSeSZn, GeSbSeSSn, GeSbTeSIn, GeSbTeSGa, GeSbTeSAl, GeSbTeSTl, GeSbTeSZn, GeSbTeSSn, GeSbSeInGa, GeSbSeInAl, GeSbSeInTl, GeSbSeInZn, GeSbSeInSn, GeSbSeGaAl, GeSbSeGaTl, GeSbSeGaZn, GeSbSeGaSn, GeSbSeAlTl, GeSbSeAlZn, GeSb SeAlSn, GeSbSeTlZn, GeSbSeTlSn, or GeSbSeZnSn.

In an implementation, the first through sixth phase-change layers 140 , 240 , 340 , 440 , 540 and 640 may include GeSbTe (GST).

Referring to FIGS. 2 A through 2 C , the first memory cell MC 1 and the second memory cell MC 2 may be spaced apart from each other in the second direction Y.

A first air gap AG 1 may be between the first memory cell MC 1 and the second memory cell MC 2 . The first air gap AG 1 may electrically insulate the first memory cell MC 1 and the second memory cell MC 2 . The first air gap AG 1 may be under a first air gap support layer SL 1 (e.g., the first air gap AG 1 may be between the substrate 100 and the first air gap support layer SL 1 in the third direction Z).

In an implementation, the first air gap AG 1 may overlap the first and second phase-change layers 140 and 240 in the second direction Y. In an implementation, the first air gap AG 1 may completely overlap the first and second phase-change layers 140 and 240 in the second direction Y. In an implementation, at least part of sidewalls of the first and second upper electrodes 150 and 250 may overlap the first air gap support layer SL 1 in the second direction Y. In an implementation, the first air gap AG 1 may be between the first and second phase-change layers 140 and 240 in the second direction Y. In an implementation, the first air gap AG 1 may completely cover sides of the first and second phase-change layers 140 and 240 in the second direction Y. In an implementation, at least part of sidewalls of the first and second upper electrodes 150 and 250 may be covered by the first air gap support layer SL 1 in the second direction Y.

The first air gap support layer SL 1 may be on the first air gap AG 1 to overlap the first air gap AG 1 in the third direction Z. The first air gap support layer SL 1 may be between the first memory cell MC 1 and the second memory cell MC 2 . The first air gap support layer SL 1 may help support the first middle conductive line BL 1 on the first air gap support layer SL 1 .

An upper surface MC 1 _us (e.g., surface facing away from the substrate 100 in the third direction Z) of the first memory cell MC 1 , an upper surface MC 2 _us of the second memory cell MC 2 , and an upper surface SL 1 _us of the first air gap support layer SL 1 may lie in the same plane (e.g., may be coplanar).

The first air gap support layer SL 1 may include, e.g., silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), SiOC, SiCN, or SiBN.

A first insulating layer IL 1 may be between the first air gap AG 1 and the first and second memory cells MC 1 and MC 2 . The first insulating layer IL 1 may be along profiles of the first memory cell MC 1 , the second memory cell MC 2 , and the interlayer insulating film 105 . For example, the first insulating layer IL 1 may be conformally formed on surfaces of the first memory cell MC 1 , the second memory cell MC 2 , and the interlayer insulating film 105 .

In an implementation, the first insulating layer IL 1 may be along profiles of the first memory cell MC 1 , the second memory cell MC 2 , and a fifth air gap support layer SL 5 .

The first insulating layer IL 1 may overlap the first and second OTS layers 120 and 220 in the second direction Y. The first insulating layer IL 1 may include, e.g., silicon nitride (SiN).

The fourth memory cell MC 4 and the fifth memory cell MC 5 may be on the first middle conductive line BL 1 . The fourth memory cell MC 4 and the fifth memory cell MC 5 may overlap the first memory cell MC 1 and the second memory cell MC 2 in the third direction Z, respectively. The fourth memory cell MC 4 and the fifth memory cell MC 5 may be spaced apart from each other in the second direction Y.

A third air gap AG 3 may be between the fourth memory cell MC 4 and the fifth memory cell MC 5 . The third air gap AG 3 may electrically insulate the fourth memory cell MC 4 and the fifth memory cell MC 5 . The third air gap AG 3 may be under a third air gap support layer SL 3 .

In an implementation, the third air gap AG 3 may overlap the first air gap AG 1 in the third direction Z. The third air gap AG 3 may overlap the fourth and fifth phase-change layers 440 and 540 in the second direction Y. In an implementation, the third air gap AG 3 may completely overlap the fourth and fifth phase-change layers 440 and 540 in the second direction Y. In an implementation, at least part of sidewalls of the fourth and fifth upper electrodes 450 and 550 may overlap the third air gap support layer SL 3 in the second direction Y.

The third air gap support layer SL 3 may be on the third air gap AG 3 . The third air gap support layer SL 3 may be between the fourth memory cell MC 4 and the fifth memory cell MC 5 .

In an implementation, the third air gap support layer SL 3 may support the interlayer insulating film 305 on the third air gap support layer SL 3 . In an implementation, the third air gap support layer SL 3 may support a sixth insulating layer IL 6 on the third air gap support layer SL 3 , a sixth air gap AG 6 , and a sixth air gap support layer SL 6 .

An upper surface SL 3 _us of the third air gap support layer SL 3 may lie in the same plane as an upper surface MC 4 _us of the fourth memory cell MC 4 and an upper surface MC 5 _us of the fifth memory cell MC 5 .

The third air gap support layer SL 3 may include, e.g., silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), SiOC, SiCN, or SiBN.

A third insulating layer IL 3 may be between the third air gap AG 3 and the fourth and fifth memory cells MC 4 and MC 5 . The third insulating layer IL 3 may be along profiles of the fourth memory cells MC 4 , the fifth memory cells MC 5 , and the first middle conductive line BL 1 .

The third insulating layer IL 3 may overlap the fourth and fifth OTS layers 420 and 520 in the second direction Y. The third insulating layer IL 3 may include, e.g., silicon nitride (SiN).

Referring to FIG. 2 B , in some embodiments, the first and third air gap support layers SL 1 and SL 3 may be multilayers.

Since the third air gap support layer SL 3 may be substantially the same as the first air gap support layer SL 1 , only the first air gap support layer SL 1 will be described below.

The first air gap support layer SL 1 may include a ( 1 _ 1 ) th air gap support layer SL 1 _ 1 (e.g., first air gap support sub-layer) and a ( 1 _ 2 ) th air gap support layer SL 1 _ 2 (e.g., second air gap support sub-layer) on the ( 1 _ 1 ) th air gap support layer SL 1 _ 1 . The ( 1 _ 1 ) th air gap support layer SL 1 _ 1 may be along profiles of the first insulating layer IL 1 and the first air gap AG 1 .

The ( 1 _ 1 ) th air gap support layer SL 1 _ 1 and the ( 1 _ 2 ) th air gap support layer SL 1 _ 2 may be made of different materials. In an implementation, the ( 1 _ 1 ) th air gap support layer SL 1 _ 1 may include, e.g., silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), SiOC, SiCN, or SiBN. The ( 1 _ 2 ) th air gap support layer SL 1 _ 2 may include, e.g., silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), SiOC, SiCN, or SiBN.

Referring to FIG. 2 C , in some embodiments, a fifth air gap AG 5 may be between the first and second lower conductive lines WL 1 and WL 2 . The sixth air gap AG 6 may be between the first and second upper conductive lines WL 3 and WL 4 .

The fifth air gap AG 5 may electrically insulate the first lower conductive line WL 1 and the second lower conductive line WL 2 . Likewise, the sixth air gap AG 6 may electrically insulate the first upper conductive line WL 3 and the second upper conductive line WL 4 .

The fifth air gap support layer SL 5 and the sixth air gap support layer SL 6 may be on the fifth air gap AG 5 and the sixth air gap AG 6 , respectively. The fifth air gap support layer SL 5 may support the first insulating layer IL 1 , the first air gap AG 1 , and the first air gap support layer SL 1 .

An upper surface SL 5 _us of the fifth air gap support layer SL 5 may lie in substantially the same plane as an upper surface WL 1 _us of the first lower conductive line WL 1 and an upper surface WL 2 _us of the second lower conductive line WL 2 .

An upper surface SL 6 _us of the sixth air gap support layer SL 6 may lie in substantially the same plane as an upper surface WL 3 _us of the first upper conductive line WL 3 and an upper surface WL 4 _us of the second upper conductive line WL 4 .

Since the fifth air gap AG 5 and the fifth air gap support layer SL 5 may be substantially the same as the sixth air gap AG 6 and the sixth air gap support layer SL 6 , respectively, only the fifth air gap AG 5 and the fifth air gap support layer SL 5 will be described below.

The fifth air gap AG 5 may be under the fifth air gap support layer SL 5 . The fifth air gap AG 5 may be overlapped by the first air gap AG 1 and the third air gap AG 3 in the third direction Z.

In an implementation, the fifth air gap support layer SL 5 may be a multilayer. The fifth air gap support layer SL 5 may include a ( 5 _ 1 ) th air gap support layer SL 5 _ 1 and a ( 5 _ 2 ) th air gap support layer SL 5 _ 2 on the ( 5 _ 1 ) th air gap support layer SL 5 _ 1 .

The ( 5 _ 1 ) th air gap support layer SL 5 _ 1 and the ( 5 _ 2 ) th air gap support layer SL 5 _ 2 may be different materials. In an implementation, the ( 5 _ 1 ) th and ( 5 _ 2 ) th air gap support layers SL 5 _ 1 and SL 5 _ 2 may include, e.g., silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), SiOC, SiCN, or SiBN.

In an implementation, the fifth air gap support layer SL 5 may be a single layer. In this case, the ( 5 _ 1 ) th air gap support layer SL 5 _ 1 and the ( 5 _ 2 ) th air gap support layer SL 5 _ 2 may be the same material.

A fifth insulating layer IL 5 may be between the first and second lower conductive lines WL 1 and WL 2 and the fifth air gap AG 5 . The fifth insulating layer IL 5 may be along profiles of the first lower conductive line WL 1 , the second lower conductive line WL 2 , and the substrate 100 .

The sixth insulating layer IL 6 may be between the first and second upper conductive lines WL 3 and WL 4 and the sixth air gap AG 6 . The sixth insulating layer IL 6 may be along profiles of the first upper conductive line WL 3 , the second upper conductive line WL 4 , and the third air gap support layer SL 3 .

The fifth and sixth insulating layers IL 5 and IL 6 may include, e.g., silicon nitride (SiN).

Referring to FIGS. 3 A through 3 C , the first memory cell MC 1 and the third memory cell MC 3 may be spaced apart from each other in the first direction X.

A second air gap AG 2 may be between the first memory cell MC 1 and the third memory cell MC 3 . The second air gap AG 2 may electrically insulate the first memory cell MC 1 and the third memory cell MC 3 . The second air gap AG 2 may be disposed under a second air gap support layer SL 2 .

The second air gap AG 2 may overlap (e.g., may be between) the first and third phase-change layers 140 and 340 in the first direction X. In an implementation, the second air gap AG 2 may completely overlap (e.g., may completely cover facing sidewalls of) the first and third phase-change layers 140 and 340 in the first direction X. In an implementation, at least part of sidewalls of the first and third upper electrodes 150 and 350 may overlap the second air gap support layer SL 2 in the first direction X.

The second air gap support layer SL 2 may be on the second air gap AG 2 and may overlap the second air gap AG 2 in the third direction Z. The second air gap support layer SL 2 may support the interlayer insulating film 205 on the second air gap support layer SL 2 .

In an implementation, the second air gap support layer SL 2 may support a seventh insulating layer IL 7 on the second air gap support layer SL 2 , a seventh air gap AG 7 , and a seventh air gap support layer SL 7 .

The upper surface MC 1 _us of the first memory cell MC 1 , an upper surface MC 3 _us of the third memory cell MC 3 , and an upper surface SL 2 _us of the second air gap support layer SL 2 may lie in the same plane.

The second air gap support layer SL 2 may include, e.g., silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), SiOC, SiCN, or SiBN.

A second insulating layer IL 2 may be between the second air gap AG 2 and the first and third memory cells MC 1 and MC 3 . The second insulating layer IL 2 may be along profiles of the first memory cell MC 1 , the third memory cell MC 3 , and the first lower conductive line WL 1 . The second insulating layer IL 2 may overlap the first and third OTS layers 120 and 320 in the first direction X. The second insulating layer IL 2 may include, e.g., silicon nitride (SiN).

The fourth memory cell MC 4 and the sixth memory cell MC 6 may be on the first and second middle conductive lines BL 1 and BL 2 , respectively. The fourth memory cell MC 4 and the sixth memory cell MC 6 may overlap the first memory cell MC 1 and the third memory cell MC 3 in the third direction Z, respectively. The fourth memory cell MC 4 and the sixth memory cell MC 6 may be spaced apart from each other in the first direction X.

A fourth air gap AG 4 may be between the fourth memory MC 4 and the sixth memory cell MC 6 . The fourth air gap AG may electrically insulate the fourth memory cell MC 4 and the sixth memory cell MC 6 . The fourth air gap AG 4 may be under a fourth air gap support layer SL 4 .

The fourth air gap AG 4 may overlap the second air gap AG 2 in the third direction Z. The fourth air gap AG 4 may overlap the fourth and sixth phase-change layers 440 and 640 in the first direction X. In an implementation, the fourth air gap AG 4 may completely overlap the fourth and sixth phase-change layers 440 and 640 in the first direction X. In an implementation, at least part of sidewalls of the fourth and sixth upper electrodes 450 and 650 may overlap the fourth air gap support layer SL 4 in the first direction X.

The fourth air gap support layer SL 4 may be on the fourth air gap AG 4 . The fourth air gap support layer SL 4 may support the first upper conductive line WL 3 . An upper surface SL 4 _us of the fourth air gap support layer SL 4 may lie in the same plane as the upper surface MC 4 _us of the fourth memory cell MC 4 and an upper surface MC 6 _us of the sixth memory cell MC 6 .

The fourth air gap support layer SL 4 may include, e.g., silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), SiOC, SiCN, or SiBN.

A fourth insulating layer IL 4 may be between the fourth air gap AG 4 and the fourth and sixth memory cells MC 4 and MC 6 . The fourth insulating layer IL 4 may be along profiles of the fourth memory cells MC 4 , the sixth memory cells MC 6 , and the interlayer insulating film 205 .

In an implementation, the fourth insulating layer IL 4 may be along profiles of the fourth memory cell MC 4 , the sixth memory cell MC 6 , and the seventh air gap support layer SL 7 . The fourth insulating layer IL 4 may overlap the fourth and sixth OTS layers 420 and 620 in the first direction X. The fourth insulating layer IL 4 may include, e.g., silicon nitride (SiN).

Referring to FIG. 3 B , in some embodiments, the second air gap support layer SL 2 and the fourth air gap support layer SL 4 may be multilayers.

Since the fourth air gap support layer SL 4 may be substantially the same as the second air gap support layer SL 2 , only the second air gap support layer SL 2 will be described below.

The second air gap support layer SL 2 may include a ( 2 _ 1 ) th air gap support layer SL 2 _ 1 and a ( 2 _ 2 ) th air gap support layer SL 2 _ 2 on the ( 2 _ 1 ) th air gap support layer SL 2 _ 1 . The ( 2 _ 1 ) th air gap support layer SL 2 _ 1 may be along profiles of the second insulating layer IL 2 and the second air gap AG 2 .

The ( 2 _ 1 ) th air gap support layer SL 2 _ 1 and the ( 2 _ 2 ) th air gap support layer SL 2 _ 2 may be made of different materials. In an implementation, the ( 2 _ 1 ) th air gap support layer SL 2 _ 1 may include, e.g., silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), SiOC, SiCN, or SiBN. The ( 2 _ 2 ) th air gap support layer SL 2 _ 2 may include, e.g., silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), SiOC, SiCN, or SiBN.

Referring to FIG. 3 C , in some embodiments, the seventh air gap AG 7 may be between the first middle conductive line BL 1 and the second middle conductive line BL 2 .

The seventh air gap AG 7 may electrically insulate the first middle conductive line BL 1 and the second middle conductive line BL 2 . The seventh air gap AG 7 may overlap the second air gap AG 2 and the fourth air gap AG 4 in the third direction Z.

The seventh air gap support layer SL 7 may be on the seventh air gap AG 7 . The seventh air gap support layer SL 7 may support the fourth insulating layer IL 4 , the fourth air gap AG 4 , and the fourth air gap support layer SL 4 .

An upper surface SL 7 _us of the seventh air gap support layer SL 7 may lie in substantially the same plane as an upper surface BL 1 _us of the first middle conductive line BL 1 and an upper surface BL 2 _us of the second middle conductive line BL 2 .

In an implementation, the seventh air gap support layer SL 7 may be a multilayer. In an implementation, the seventh air gap support layer SL 7 may include a ( 7 _ 1 ) th air gap support layer SL 7 _ 1 and a ( 7 _ 2 ) th air gap support layer SL 7 _ 2 on the ( 7 _ 1 ) th air gap support layer SL 7 _ 1 .

The ( 7 _ 1 ) th air gap support layer SL 7 _ 1 may be along profiles of the first and second middle conductive lines BL 1 and BL 2 and the second air gap support layer SL 2 .

The ( 7 _ 1 ) th air gap support layer SL 7 _ 1 and the ( 7 _ 2 ) th air gap support layer SL 7 _ 2 may be different materials. In an implementation, the ( 7 _ 1 ) th air gap support layer SL 7 _ 1 and the ( 7 _ 2 ) th air gap support layer SL 7 _ 2 may include, e.g., silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), SiOC, SiCN, or SiBN.

In an implementation, the seventh air gap support layer SL 7 may be a single layer. In this case, the ( 7 _ 1 ) th air gap support layer SL 7 _ 1 and the ( 7 _ 2 ) th air gap support layer SL 7 _ 2 may be the same material.

A method of fabricating a semiconductor memory device according to embodiments of the present disclosure will now be described with reference to FIGS. 4 through 39 .

FIGS. 4 through 11 are views of stages in a method of fabricating a semiconductor memory device according to embodiments of the present disclosure. FIG. 4 is a layout view of a stage in the method of fabricating a semiconductor memory device according to the embodiments. FIG. 5 is a cross-sectional view taken along line C-C of FIG. 4 .

Referring to FIGS. 4 and 5 , a first lower conductive line WL 1 and a second lower conductive line WL 2 may be formed on a substrate 100 .

The first lower conductive line WL 1 and the second lower conductive line WL 2 may extend (e.g., lengthwise) in the first direction X. The first lower conductive line WL 1 and the second lower conductive line WL 2 may be spaced apart from each other in the second direction Y.

Referring to FIG. 6 , a fifth insulating layer IL 5 may be formed along profiles of (e.g., may be formed conformally on) the substrate 100 , the first lower conductive line WL 1 , and the second lower conductive line WL 2 .

The fifth insulating layer IL 5 may be formed using, e.g., chemical vapor deposition (CVD), physics vapor deposition (PVD), or atomic layer deposition (ALD). In an implementation, the fifth insulating layer IL 5 may be formed using ALD.

Referring to FIG. 7 , a first mold carbon layer MCL 1 may be formed on the fifth insulating layer IL 5 .

The first mold carbon layer MCL 1 may be formed by depositing two or more kinds of monomers containing carbon (C) in a CVD chamber at 50 to 100° C. The first mold carbon layer MCL 1 may be a polymer including carbon (C), hydrogen (H), oxygen (O), and nitrogen (N). The first mold carbon layer MCL 1 may be decomposed back into monomers when applied with heat, e.g., heating at a temperature of 170° C. or higher.

Referring to FIG. 8 , a part of the first mold carbon layer MCL 1 may be removed.

The first mold carbon layer MCL 1 may be removed by performing a heat treatment process. The heat treatment process may include applying heat, e.g., heating at a temperature of 170 to 300° C. The heat treatment process may help reduce damage to the fifth insulating layer IL 5 in the process of removing the first mold carbon layer MCL 1 .

Referring to FIG. 9 , a ( 5 _ 1 ) th air gap support layer SL 5 _ 1 and a ( 5 _ 2 ) th air gap support layer SL 5 _ 2 may be formed on the fifth insulating layer IL 5 and the first mold carbon layer MCL 1 .

In an implementation, the ( 5 _ 1 ) th air gap support layer SL 5 _ 1 may be formed along profiles of the fifth insulating layer IL 5 and the first mold carbon layer MCL 1 . The ( 5 _ 2 ) th air gap support layer SL 5 _ 2 may be formed on the ( 5 _ 1 ) th air gap support layer SL 5 _ 1 .

The ( 5 _ 1 ) th air gap support layer SL 5 _ 1 and the ( 5 _ 2 ) th air gap support layer SL 5 _ 2 may be made of the same material or may be made of different materials.

Referring to FIG. 10 , a fifth air gap AG 5 may be formed by removing the first mold carbon layer MCL 1 .

The first mold carbon layer MCL 1 may be removed by performing a heat treatment process. The heat treatment process may include applying heat, e.g., heating at a temperature of 170 to 300° C. The use of the heat treatment process may help reduce damage to the fifth insulating layer IL 5 in the process of removing the first mold carbon layer MCL 1 .

Referring to FIG. 11 , a fifth air gap support layer SL 5 may be formed by partially removing the ( 5 _ 1 ) th air gap support layer SL 5 _ 1 , the ( 5 _ 2 ) th air gap support layer SL 5 _ 2 , and the fifth insulating layer IL 5 .

The ( 5 _ 1 ) th air gap support layer SL 5 _ 1 , the ( 5 _ 2 ) th air gap support layer SL 5 _ 2 , and the fifth insulating layer IL 5 may be removed using a chemical mechanical polishing (CMP) process.

Therefore, an upper surface WL 1 _us of the first lower conductive line WL 1 , an upper surface SL 5 _us of the fifth air gap support layer SL 5 , and an upper surface WL 2 _us of the second lower conductive line WL 2 may lie in substantially the same plane.

Referring to FIGS. 9 through 11 , the fifth air gap AG 5 may be formed after the ( 5 _ 2 ) th air gap support layer SL 5 _ 2 is formed. In an implementation, it may be formed after only the ( 5 _ 1 ) th air gap support layer SL 5 _ 1 is formed or may be formed after the fifth air gap support layer SL 5 is formed.

FIGS. 12 through 20 are views of stages in a method of fabricating a semiconductor memory device according to the embodiments of the present disclosure.

FIG. 12 is a layout view of a stage in a method of fabricating a semiconductor memory device according to the embodiments. FIG. 13 is a cross-sectional view taken along line D-D of FIG. 12 .

Referring to FIGS. 12 and 13 , a first memory cell MC 1 may be formed on the first lower conductive line WL 1 .

A second memory cell MC 2 may be formed on the second lower conductive line WL 2 . A third memory cell MC 3 (spaced apart from the first memory cell MC 1 in the first direction X) may be formed on the first lower conductive line WL 1 . The first memory cell MC 1 and the second memory cell MC 2 may be spaced apart from each other in the second direction Y.

Referring to FIG. 14 , a first insulating layer IL 1 may be formed along profiles of the first and second memory cells MC 1 and MC 2 and the fifth air gap support layer SL 5 .

The first insulating layer IL 1 may be formed using CVD, PVD, or ALD. In an implementation, the first insulating layer IL 1 may be formed using ALD.

Referring to FIG. 15 , a second mold carbon layer MCL 2 may be formed on the first insulating layer

The second mold carbon layer MCL 2 may be the same material as the first mold carbon layer (e.g., MCL 1 of FIG. 7 ).

Referring to FIG. 16 , a part of the second mold carbon layer MCL 2 may be removed.

The second mold carbon layer MCL 2 may be removed using a heat treatment process. The heat treatment process may include applying heat, e.g., heating at a temperature of 170 to 300° C. The use of the heat treatment process may help reduce damage to the first insulating layer IL 1 in the process of removing the second mold carbon layer MCL 2 .

Referring to FIG. 17 , a ( 1 _ 1 ) th air gap support layer SL 1 _ 1 may be formed along profiles of the second mold carbon layer MCL 2 and the first and second memory cells MC 1 and MC 2 .

Referring to FIG. 18 , a ( 1 _ 2 ) th air gap support layer SL 1 _ 2 may be formed on the ( 1 _ 1 ) th air gap support layer SL 1 _ 1 .

The ( 1 _ 1 ) th air gap support layer SL 1 _ 1 and the ( 1 _ 2 ) th air gap support layer SL 1 _ 2 may be made of the same material or may be made of different materials.

Referring to FIG. 19 , a first air gap AG 1 may be formed by removing the second mold carbon layer MCL 2 .

The second mold carbon layer MCL 2 may be removed using a heat treatment process. The heat treatment process may include applying heat, e.g., heating at a temperature of 170 to 300° C. The use of the heat treatment process may reduce damage to the first insulating layer IL 1 in the process of removing the second mold carbon layer MCL 2 .

Referring to FIG. 20 , a first air gap support layer SL 1 may be formed by partially removing the first insulating layer IL 1 , the ( 1 _ 1 ) th air gap support layer SL 1 _ 1 , and the ( 1 _ 2 ) th air gap support layer SL 1 _ 2 .

The ( 1 _ 1 ) th air gap support layer SL 1 _ 1 , the ( 1 _ 2 ) th air gap support layer SL 1 _ 2 , and the first insulating layer IL 1 may be removed using a CMP process.

In an implementation, an upper surface SL 1 _us of the first air gap support layer SL 1 may lie in substantially the same plane as an upper surface MC 1 _us of the first memory cell MC 1 and an upper surface MC 2 _us of the second memory cell MC 2 .

Referring to FIGS. 18 through 20 , the first air gap AG 1 may be formed after the ( 1 _ 2 ) th air gap support layer SL 1 _ 2 is formed. In an implementation, it may be formed after the ( 1 _ 1 ) th air gap support layer SL 1 _ 1 is formed or may be formed after the first air gap support layer SL 1 is formed.

FIGS. 21 through 30 are views of stages in a method of fabricating a semiconductor memory device according to the embodiments of the present disclosure.

FIG. 21 is a layout view of a stage in a method of fabricating a semiconductor memory device according to the embodiments. FIG. 22 is a cross-sectional view taken along line E 1 -E 1 of FIG. 21 . FIG. 23 is a cross-sectional view taken along line E 2 -E 2 of FIG. 21 . FIGS. 24 through 30 will be described based on a cross section taken along line E 2 -E 2 of FIG. 21 .

Referring to FIGS. 21 through 23 , a first middle conductive line BL 1 and a second middle conductive line BL 2 may be formed.

The first and second middle conductive lines BL 1 and BL 2 may extend in the second direction Y. The first and second middle conductive lines BL 1 and BL 2 may be spaced apart from each other in the first direction X.

Referring to FIG. 24 , a seventh insulating layer IL 7 may be formed along profiles of the first and second middle conductive lines BL 1 and BL 2 and a second air gap support layer SL 2 .

The seventh insulating layer IL 7 may be formed using CVD, PVD, or ALD. In an implementation, the seventh insulating layer IL 7 may be formed using ALD.

Referring to FIG. 25 , a third mold carbon layer MCL 3 may be formed on the seventh insulating layer IL 7 .

The third mold carbon layer MCL 3 may be the same material as the first mold carbon layer (e.g., MCL 1 of FIG. 7 ).

Referring to FIG. 26 , a part of the third mold carbon layer MCL 3 may be removed.

The third mold carbon layer MCL 3 may be removed using a heat treatment process. The heat treatment process may include applying heat, e.g., heating at a temperature of 170 to 300° C. The use of the heat treatment process may reduce damage to the seventh insulating layer IL 7 in the process of removing the third mold carbon layer MCL 3 .

Referring to FIG. 27 , a ( 7 _ 1 ) th air gap support layer SL 7 _ 1 may be formed along profiles of the third mold carbon layer MCL 3 and the first and second middle conductive lines BL 1 and BL 2 .

Referring to FIG. 28 , a ( 7 _ 2 ) th air gap support layer SL 7 _ 2 may be formed on the ( 7 _ 1 ) th air gap support layer SL 7 _ 1 .

The ( 7 _ 1 ) th air gap support layer SL 7 _ 1 and the ( 7 _ 2 ) th air gap support layer SL 7 _ 2 may be made of the same material or may be made of different materials.

Referring to FIG. 29 , a seventh air gap AG 7 may be formed by removing the third mold carbon layer MCL 3 .

The third mold carbon layer MCL 3 may be removed using a heat treatment process. The heat treatment process may include applying heat, e.g., heating at a temperature of 170 to 300° C. The use of the heat treatment process may help reduce damage to the seventh insulating layer IL 7 in the process of removing the third mold carbon layer MCL 3 .

Referring to FIG. 30 , a seventh air gap support layer SL 7 may be formed by partially removing the seventh insulating layer IL 7 , the ( 7 _ 1 ) th air gap support layer SL 7 _ 1 , and the ( 7 _ 2 ) th air gap support layer SL 7 _ 2 .

The ( 7 _ 1 ) th air gap support layer SL 7 _ 1 , the ( 7 _ 2 ) th air gap support layer SL 7 _ 2 , and the seventh insulating layer IL 7 may be removed using a CMP process.

In an implementation, an upper surface SL 7 _us of the seventh air gap support layer SL 7 may lie in substantially the same plane as an upper surface BL 1 _us of the first middle conductive line BL 1 and an upper surface BL 2 _us of the second middle conductive line BL 2 .

Referring to FIGS. 28 through 30 , the seventh air gap AG 7 may be formed after the ( 7 _ 2 ) th air gap support layer SL 7 _ 2 is formed. In an implementation, it may be formed after the ( 7 _ 1 ) th air gap support layer SL 7 _ 1 is formed or may be formed after the seventh air gap support layer SL 7 is formed.

FIGS. 31 through 39 are views of stages in a method of fabricating a semiconductor memory device according to the embodiments of the present disclosure.

FIG. 31 is a layout view of a stage in a method of fabricating a semiconductor memory device according to the embodiments. FIG. 32 is a cross-sectional view taken along line F-F of FIG. 31 .

Referring to FIGS. 31 and 32 , a fourth memory cell MC 4 may be formed on the first middle conductive line BL 1 .

A sixth memory cell MC 6 (spaced apart from the fourth memory cell MC 4 in the first direction X) may be formed on the second middle conductive line BL 2 . A fifth memory cell MC 5 (spaced apart from the fourth memory cell MC 4 in the second direction Y) may be formed on the first middle conductive line BL 1 .

Referring to FIG. 33 , a fourth insulating layer IL 4 may be formed along profiles of the fourth and sixth memory cells MC 4 and MC 6 and the seventh air gap support layer SL 7 .

The fourth insulating layer IL 4 may be formed using CVD, PVD, or ALD. In an implementation, the fourth insulating layer IL 4 may be formed using ALD.

Referring to FIG. 34 , a fourth mold carbon layer MCL 4 may be formed on the fourth insulating layer IL 4 .

The fourth mold carbon layer MCL 4 may be the same material as the first mold carbon layer (e.g., MCL 1 of FIG. 7 ).

Referring to FIG. 35 , a part of the fourth mold carbon layer MCL 4 may be removed.

The fourth mold carbon layer MCL 4 may be removed using a heat treatment process. The heat treatment process may include applying heat, e.g., heating at a temperature of 170 to 300° C. The use of the heat treatment process may help reduce damage to the fourth insulating layer IL 4 in the process of removing the fourth mold carbon layer MCL 4 .

Referring to FIG. 36 , a ( 4 _ 1 ) th air gap support layer SL 4 _ 1 may be formed along profiles of the fourth mold carbon layer MCL 4 and the fourth and sixth memory cells MC 4 and MC 6 . A ( 4 _ 2 ) th air gap support layer SL 4 _ 2 may be formed on the ( 4 _ 1 ) th air gap support layer SL 4 _ 1 .

The ( 4 _ 1 ) th air gap support layer SL 4 _ 1 and the ( 4 _ 2 ) th air gap support layer SL 4 _ 2 may be made of the same material or may be made of different materials.

Referring to FIG. 37 , a fourth air gap AG 4 may be formed by removing the fourth mold carbon layer MCL 4 .

The fourth mold carbon layer MCL 4 may be removed using a heat treatment process. The heat treatment process may include applying heat, e.g., heating at a temperature of 170 to 300° C. The use of the heat treatment process may help reduce damage to the fourth insulating layer IL 4 in the process of removing the fourth mold carbon layer MCL 4 .

Referring to FIG. 38 , a fourth air gap support layer SL 4 may be formed by partially removing the fourth insulating layer IL 4 , the ( 4 _ 1 ) th air gap support layer SL 4 _ 1 , and the ( 4 _ 2 ) th air gap support layer SL 4 _ 2 .

The ( 4 _ 1 ) th air gap support layer SL 4 _ 1 , the ( 4 _ 2 ) th air gap support layer SL 4 _ 2 , and the fourth insulating layer IL 4 may be removed using a CMP process.

In an implementation, an upper surface SL 4 _us of the fourth air gap support layer SL 4 may lie in substantially the same plane as an upper surface MC 4 _us of the fourth memory cell MC 4 and an upper surface MC 6 _us of the sixth memory cell MC 6 .

Referring to FIGS. 36 through 38 , the fourth air gap AG 4 may be formed after the ( 4 _ 2 ) th air gap support layer SL 4 _ 2 is formed. In an implementation, it may be formed after the ( 4 _ 1 ) th air gap support layer SL 4 _ 1 is formed or may be formed after the fourth air gap support layer SL 4 is formed.

Referring to FIG. 39 , a first upper conductive line WL 3 may be formed on the fourth memory cell MC 4 and the sixth memory cell MC 6 . In an implementation, a second upper conductive line WL 4 spaced apart from the first upper conductive line WL 3 in the second direction Y may be formed.

In an implementation, a sixth air gap (e.g., AG 6 of FIG. 2 C ) may be formed between the first upper conductive line WL 3 and the second upper conductive line WL 4 . The process of forming the sixth air gap may be the same as the process of forming the fifth air gap (e.g., AG 5 of FIG. 2 C ).

One or more embodiments may provide a semiconductor memory device including an air gap that electrically insulates word lines, bit lines, or memory cells.

One or more embodiments may provide a semiconductor memory device with improved performance and reliability.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.