Display driver and semiconductor device

1. Field

The present invention relates to a display driver for driving a display device in accordance with a video signal, and a semiconductor device including the display driver.

2. Description of the Related Art

As display drivers for driving display devices, such as liquid crystal display panels and organic EL display panels, a display driver that includes a gradation voltage generation circuit and DA converters and output amplifiers the numbers of which correspond to the number of output channels is known (see, for example, Japanese Patent Application Laid-Open No. 2011-154386).

The gradation voltage generation circuit includes a ladder resistor. The ladder resistor divides a power voltage into a plurality of voltages, and outputs the voltages as a plurality of gradation voltages. The DA converters selectively output gradation voltages corresponding to luminance levels represented by image data, out of the plurality of gradation voltages. The output amplifiers apply data voltages, which are obtained by buffering the voltages outputted from the DA converters, to source lines of the display device.

By the way, portable information terminal devices, e.g., smartphones and the like, have a normal mode in which no limitation is imposed on its function and performance, and a power save mode in which limitations are imposed on a part of the function or performance to reduce a consumption of a battery, as operation modes. For example, in the power save mode, the display driver performs display with a reduced number of display gradations, in order to reduce an electric power consumption.

However, even in the display with a reduced number of display gradations, each circuit of the display driver has to operate. For example, since the gradation voltage generation circuit is constituted of three systems of circuits that generate, e.g., 256 levels of gradation voltages having gamma correction characteristics corresponding to each color (red, green, or blue), in actual fact, even if the number of display gradations is reduced, a current flows through the ladder resistor included in each circuit.

Therefore, even in the power save mode, it is difficult to significantly reduce an electric power consumption.

The present invention aims at providing a display driver and a semiconductor device that can significantly reduce an electric power consumption.

A display driver according to the present invention includes: a plurality of gradation voltage generation circuits each configured to generate a plurality of gradation voltages; first to n-th DA converter circuits each configured to select and output a gradation voltage corresponding to a luminance level indicated by pixel data from the plurality of gradation voltages generated by one of the gradation voltage generation circuits; first to n-th amplifiers configured to independently amplify n gradation voltages outputted from the first to n-th DA converter circuits, to generate n amplified gradation voltages; and an output selector configured to receive a mode signal indicating a normal mode or a power save mode and to output the n amplified gradation voltages from n output terminals, respectively, when the mode signal indicates said normal mode. When the mode signal indicates the power save mode, the plurality of gradation voltage generation circuits, except for one gradation voltage generation circuit, stop generating the gradation voltages. when the mode signal indicates the power save mode, in each of divisions into which the n amplified gradation voltages are divided into groups each containing k (k is an integer of less than n) amplified gradation voltages, the output selector outputs one of k amplified gradation voltages from k output terminals, and opens an output terminal of each of the amplifiers, except for an amplifier configured to generate the one of k amplified gradation voltages, out of k amplifiers configured to generate the k amplified gradation voltages.

A semiconductor device according to the present invention includes a display driver configured to drive a display device having n number (n is an integer of 2 or more) of data lines. The semiconductor device includes: a plurality of gradation voltage generation circuits each configured to generate a plurality of gradation voltages; first to n-th DA converter circuits each configured to select and output a gradation voltage corresponding to a luminance level indicated by pixel data from the plurality of gradation voltages generated by one of the gradation voltage generation circuits; first to n-th amplifiers configured to independently amplify n gradation voltages outputted from the first to n-th DA converter circuits, to generate n amplified gradation voltages; and an output selector configured to receive a mode signal indicating a normal mode or a power save mode and to output the n amplified gradation voltages from n output terminals, respectively, when the mode signal indicates said normal mode. When the mode signal indicates the power save mode, the plurality of gradation voltage generation circuits, except for one gradation voltage generation circuit, stop generating the gradation voltages. when the mode signal indicates the power save mode, in each of divisions into which the n amplified gradation voltages are divided into groups each containing k (k is an integer of less than n) amplified gradation voltages, the output selector outputs one of k amplified gradation voltages from k output terminals, and opens an output terminal of each of the amplifiers, except for an amplifier configured to generate the one of k amplified gradation voltages, out of k amplifiers configured to generate the k amplified gradation voltages.

In the power save mode, the display driver according to the present invention stops the operation of the plurality of gradation voltage generation circuits, except for the one gradation voltage generation circuit. In the power save mode, in each of divisions into which the n amplified gradation voltages, in which the n gradation voltages obtained by DA conversions have been amplified, are divided into groups each containing k (k is an integer of less than n) amplified gradation voltages, one of k amplified gradation voltages is outputted from the k output terminals. Furthermore, the output terminal of each amplifier, except for the amplifier configured to generate the one amplified gradation voltage described above, of the k amplifiers configured to generate the k amplified gradation voltages is opened.

According to the above-described configuration, in the power save mode, the gradation voltage generation circuits, except for the one gradation voltage generation circuit, stop operating, and therefore, an output current outputted from the n amplifiers is significantly reduced, thus allowing a significant reduction in an electric power consumption.

FIG. 1 is a block diagram showing a configuration of a display unit 100 including a display driver according to the present invention;

FIG. 2 is a block diagram showing an internal configuration of a drive voltage output part 132 ;

FIG. 3 is a circuit diagram of each of a red gradation voltage generation circuit GVR, a green gradation voltage generation circuit GVG, and a blue gradation voltage generation circuit GVB;

FIG. 4 is a block diagram showing an example of an internal configuration of a voltage conversion output part CVP;

FIG. 5 is an equivalent circuit diagram showing an internal state of the drive voltage output part 132 in a power save mode;

FIG. 6 is a drawing showing the internal configuration of the voltage conversion output part CVP adopted in performing monochromatic color display in the power save mode;

FIG. 7 is a time chart for explaining an operation of an output selector SELa;

FIG. 8 is a circuit diagram showing an internal state of the output selector SELa in a first cycle CYC 1 ;

FIG. 9 is a circuit diagram showing an internal state of the output selector SELa in a second cycle CYC 2 ;

FIG. 10 is a circuit diagram showing an internal state of the output selector SELa in a third cycle CYC 3 ; and

FIG. 11 is a circuit diagram showing an internal state of the output selector SELa in a fourth cycle CYC 4 .

An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a display unit 100 including a display driver according to the present invention. As shown in FIG. 1 , the display unit 100 includes a drive controller 11 , a scan driver 12 , a data driver 13 , and a display device 20 .

The display device 20 is constituted of, for example, an organic EL panel or the like. The display device 20 includes horizontal scan lines S 1 to Sm (m is an integer of 2 or more) extending in a horizontal direction of a two-dimensional screen, and data lines D 1 to Dn (n is an integer of 2 or more) extending in a vertical direction of the two-dimensional screen. Red display cells for displaying a red color, green display cells for displaying a green color, and blue display cells for displaying a blue color are formed in areas (areas enclosed by broken lines) at respective intersections of the horizontal scan lines and the data lines. In the display device 20 , the display cells are arranged in order of, for example, a red display cell, a green display cell, a blue display cell, a green display cell, a red display cell, a green display cell, a blue display cell, a green display cell, . . . , along each horizontal scan line. At this time, the four display cells of “a red display cell, a green display cell, a blue display cell, and a green display cell” that are adjacently arranged in the horizontal direction of the two-dimensional screen constitute one pixel.

The horizontal scan lines S 1 to Sm are connected to the scan driver 12 . The data lines D 1 to Dn are connected to the data driver 13 .

The drive controller 11 detects a horizontal synchronization signal from a video signal VD, and supplies the scan driver 12 with the horizontal synchronization signal. The drive controller 11 generates an image data signal PD including a series of pixel data pieces that represent luminance levels of the pixels as, e.g., 8-bit luminance gradations, on the basis of the video signal VD, and supplies the data driver 13 with the image data signal PD.

The scan driver 12 sequentially applies a horizontal scan pulse to each of the horizontal scan lines S 1 to Sm of the display device 20 at synchronized timing with the horizontal synchronization signal supplied from the drive controller 11 .

The data driver 13 is formed in a semiconductor IC (integrated circuit) chip.

As shown in FIG. 1 , the data driver 13 includes a data capture part 131 and a drive voltage output part 132 .

The data capture part 131 captures pixel data pieces included in the image data signal PD on a horizontal scan line basis, in other words, by a number of n. The data capture part 131 supplies the drive voltage output part 132 with the captured n pixel data pieces as pixel data P 1 to Pn.

The drive voltage output part 132 generates drive voltages G 1 to Gn having voltage levels corresponding to the luminance levels represented by pixel data P, on the basis of the pixel data P 1 to Pn, and applies the drive voltages G 1 to Gn to the data lines D 1 to Dn of the display device 20 , respectively.

FIG. 2 is a block diagram showing the internal configuration of the drive voltage output part 132 .

In FIG. 2 , power circuits PWR, PWG, and PWB receive a mode signal MOD from a controller of an information processing device, such as a smartphone or a cellular phone, having the display unit 100 . When the mode signal MOD indicates a normal mode, the power circuit PWR generates a power potential VDD, a ground potential VSS, and reference gradation potentials VR 1 to VR 8 . Note that the reference gradation potentials VR 1 to VR 8 are eight potentials different from each other that are set within the range between the power potential VDD and the ground potential VSS in accordance with gamma correction characteristics corresponding to a red color.

The power circuit PWR supplies a red gradation voltage generation circuit GVR with the generated power potential VDD, ground potential VSS, and reference gradation potentials VR 1 to VR 8 .

When the mode signal MOD indicates a power save mode, the power circuit PWR stops generating the reference gradation potentials VR 1 to VR 8 , and supplies the red gradation voltage generation circuit GVR only with the power potential VDD and the ground potential VSS.

When the mode signal MOD indicates the normal mode, the power circuit PWG generates a power potential VDD, a ground potential VSS, and reference gradation potentials VG 1 to VG 8 . Note that, the reference gradation potentials VG 1 to VG 8 are eight potentials different from each other that are set within the range between the power potential VDD and the ground potential VSS in accordance with gamma correction characteristics corresponding to a green color.

The power circuit PWG supplies a green gradation voltage generation circuit GVG with the generated power potential VDD, ground potential VSS, and reference gradation potentials VG 1 to VG 8 .

When the mode signal MOD indicates the power save mode, the power circuit PWG stops generating the reference gradation potentials VG 1 to VG 8 , the power potential VDD, and the ground potential VSS. In other words, in the power save mode, the power circuit PWG is in an operation stop state.

When the mode signal MOD indicates the normal mode, the power circuit PWB generates a power potential VDD, a ground potential VSS, and reference gradation potentials VB 1 to VB 8 . Note that the reference gradation potentials VB 1 to VB 8 are eight potentials different from each other that are set within the range between the power potential VDD and the ground potential VSS in accordance with gamma correction characteristics corresponding to a blue color.

The power circuit PWB supplies a blue gradation voltage generation circuit GVB with the generated power potential VDD, ground potential VSS, and reference gradation potentials VB 1 to VB 8 .

When the mode signal MOD indicates the power save mode, the power circuit PWB stops generating the reference gradation potentials VB 1 to VB 8 , the power potential VDD, and the ground potential VSS. In other words, in the power save mode, the power circuit PWB is in an operation stop state.

As shown in FIG. 3 , each of the red gradation voltage generation circuit GVR, the green gradation voltage generation circuit GVG, and the blue gradation voltage generation circuit GVB includes a ladder resistor LD in which 255 or more resistors are connected in series.

The ladder resistor LD receives the power potential VDD at one end, and receives the ground potential VSS at the other end. Furthermore, the ladder resistor LD receives the reference gradation potentials VR 1 to VR 8 (VG 1 to VG 8 , or VB 1 to VB 8 ) at eight nodes of a plurality of nodes at which the resistors are connected to each other.

In the normal mode, the red gradation voltage generation circuit GVR obtains voltages occurring at 256 nodes of the ladder resistor LD by the application of the power potential VDD, the reference gradation potentials VR 1 to VR 8 , and the ground potential VSS, as gradation voltages Vr 1 to Vr 256 . The red gradation voltage generation circuit GVR supplies a voltage conversion output part CVP with the gradation voltages Vr 1 to Vr 256 , as a first gradation voltage group in which a gamma correction has been applied to the red color.

In the power save mode, the red gradation voltage generation circuit GVR supplies the voltage conversion output part CVP only with the two gradation voltages Vr 1 and Vr 256 out of the gradation voltages Vr 1 to Vr 256 .

In the normal mode, the green gradation voltage generation circuit GVG obtains voltages occurring at 256 nodes of the ladder resistor LD by the application of the power potential VDD, the reference gradation potentials VG 1 to VG 8 , and the ground potential VSS, as gradation voltages Vg 1 to Vg 256 . At this time, the green gradation voltage generation circuit GVG supplies the voltage conversion output part CVP with the gradation voltages Vg 1 to Vg 256 , as a second gradation voltage group in which a gamma correction has been applied to the green color.

In the power save mode, the green gradation voltage generation circuit GVG stops supplying the voltage conversion output part CVP with the gradation voltages Vg 1 to Vg 256 .

In the normal mode, the blue gradation voltage generation circuit GVB obtains voltages occurring at 256 nodes of the ladder resistor LD by the application of the power potential VDD, the reference gradation potentials VB 1 to VB 8 , and the ground potential VSS, as gradation voltages Vb 1 to Vb 256 . At this time, the blue gradation voltage generation circuit GVB supplies the voltage conversion output part CVP with the gradation voltages Vb 1 to Vb 256 , as a third gradation voltage group in which a gamma correction has been applied to the blue color.

In the power save mode, the blue gradation voltage generation circuit GVB stops supplying the voltage conversion output part CVP with the gradation voltages Vb 1 to Vb 256 .

The voltage conversion output part CVP selects a gradation voltage corresponding to the luminance level represented by the pixel data P, on the basis of each of the pixel data P 1 to Pn, from one of the first to third gradation voltage groups (Vr 1 to Vr 256 , Vg 1 to Vg 256 , and Vb 1 to Vb 256 ). Next, as described above, the voltage conversion output part CVP amplifies each of the n gradation voltages independently, to obtain n amplified gradation voltages. The voltage conversion output part CVP outputs n number amplified gradation voltages as drive voltages G 1 to Gn. The drive voltages G 1 to Gn are applied to the data lines D 1 to Dn of the display device 20 , respectively.

FIG. 4 is a block diagram showing an example of the internal configuration of the voltage conversion output part CVP.

The voltage conversion output part CVP as illustrated in FIG. 4 includes an n/4 number of voltage conversion output blocks BK, which are obtained by dividing n number channels corresponding to the drive voltages G 1 to Gn by four that is the number of the display cells (the red display cell, the green display cell, the blue display cell, and the green display cell) constituting the one pixel.

The voltage conversion output blocks BK have the same internal configuration. Taking the voltage conversion output block BK corresponding to the drive voltages G 1 to G 4 as an example, the internal configuration thereof will be described below.

A DA converter circuit DCa is connected to the red gradation voltage generation circuit GVR. The DA converter circuit DCa selects a gradation voltage corresponding to the luminance level of the pixel data P 1 from the gradation voltages Vr 1 to Vr 256 , which belong to the first gradation voltage group to which a red gamma correction has been applied. The DA converter circuit DCa supplies an amplifier APa with the selected gradation voltage as a gradation voltage Ua.

The amplifier APa amplifies the gradation voltage Ua with, for example, a gain of 1, and supplies an output selector SEL with the amplified voltage as an amplified gradation voltage Qa.

A DA converter circuit DCb is connected to the green gradation voltage generation circuit GVG. The DA converter circuit DCb selects a gradation voltage corresponding to the luminance level of the pixel data P 2 from the gradation voltages Vg 1 to Vg 256 , which belong to the second gradation voltage group to which a green gamma correction has been applied. The DA converter circuit DCb supplies an amplifier APb with the selected gradation voltage as a gradation voltage Ub.

The amplifier APb amplifies the gradation voltage Ub with, for example, a gain of 1, and supplies the output selector SEL with the amplified voltage as an amplified gradation voltage Qb.

A DA converter circuit DCc is connected to the blue gradation voltage generation circuit GVB. The DA converter circuit DCc selects a gradation voltage corresponding to the luminance level of the pixel data P 3 from the gradation voltages Vb 1 to Vb 256 , which belong to the third gradation voltage group to which a blue gamma correction has been applied. The DA converter circuit DCc supplies an amplifier APc with the selected gradation voltage as a gradation voltage Uc.

The amplifier APc amplifies the gradation voltage Uc with, for example, a gain of 1, and supplies the output selector SEL with the amplified voltage as an amplified gradation voltage Qc.

A DA converter circuit DCd is connected to the green gradation voltage generation circuit GVG. The DA converter circuit DCd selects a gradation voltage corresponding to the luminance level of the pixel data P 4 from the gradation voltages Vg 1 to Vg 256 , which belong to the second gradation voltage group to which a green gamma correction has been applied. The DA converter circuit DCd supplies an amplifier APd with the selected gradation voltage as a gradation voltage Ud.

The amplifier APd amplifies the gradation voltage Ud with, for example, a gain of 1, and supplies the output selector SEL with the amplified voltage as an amplified gradation voltage Qd.

The output selector SEL has output terminals Y 1 to Y 4 that are connected to the four data lines D of the display device 20 , respectively.

In the normal mode, the output selector SEL associates the amplified gradation voltages Qa to Qd with the output terminals Y 1 to Y 4 so as to correspond to the arrangements of the red display cell, the green display cell, and the blue display cell arranged along each of the horizontal scan lines S formed on the display device 20 .

The output selector SEL outputs a voltage associated with the output terminal Y 1 , out of the amplified gradation voltages Qa, Qb, Qc, and Qd, as a drive voltage G 1 from the output terminal Y 1 , and outputs a voltage associated with the output terminal Y 2 as a drive voltage G 2 from the output terminal Y 2 . Furthermore, the output selector SEL outputs a voltage associated with the output terminal Y 3 , out of the amplified gradation voltages Qa, Qb, Qc, and Qd, as a drive voltage G 3 from the output terminal Y 3 , and outputs a voltage associated with the output terminal Y 4 as a drive voltage G 4 from the output terminal Y 4 .

For example, when the correspondences between the amplified gradation voltages Qa, Qb, Qc, and Qd and the output terminals Y 1 to Y 4 are as follows:

Qa: Y 4

Qb: Y 3

Qc: Y 2

Qd: Y 1

the output selector SEL outputs the amplified gradation voltage Qa from the output terminal Y 4 as the drive voltage G 4 , and outputs the amplified gradation voltage Qb from the output terminal Y 3 as the drive voltage G 3 . Furthermore, the output selector SEL outputs the amplified gradation voltage Qc from the output terminal Y 2 as the drive voltage G 2 , and outputs the amplified gradation voltage Qd from the output terminal Y 1 as the drive voltage G 1 .

On the other hand, in the power save mode, the output selector SEL outputs the amplified gradation voltage Qa out of the amplified gradation voltages Qa, Qb, Qc, and Qd from the output terminals Y 1 to Y 4 as the drive voltages G 1 to G 4 .

As described above, each voltage conversion output block BK includes DA converter circuits DCa to DCd for four channels and amplifiers APa to APd. In other words, the voltage conversion output part CVP includes first to n-th DA converter circuits (DC) for n channels and first to n-th amplifiers (AP).

The internal state of the drive voltage output part 132 , when the mode signal MOD indicates the power save mode, will be described below with reference to an equivalent circuit shown in FIG. 5 . The equivalent circuit shown in FIG. 5 omits circuits that are put into an operation stop state in the power save mode and parts of the circuit that are not involved with the power save mode, in the configuration shown in FIGS. 2 and 4 .

In the power save mode, the power circuits PWG and PWB, the green gradation voltage generation circuit GVG, and the blue gradation voltage generation circuit GVB are put into an operation stop state. Therefore, each of the DA converter circuits DCb, DCc, and DCd and the amplifiers APb, APc, and APd, included in each voltage conversion output block BK, has a fixed output level.

In the power save mode, the power circuit PWR generates the power potential VDD and the ground potential VSS, and supplies the red gradation voltage generation circuit GVR with the power potential VDD and the ground potential VSS, while it stops generating the reference gradation potentials VR 1 to VR 8 .

The red gradation voltage generation circuit GVR thereby supplies the DA converter circuit DCa of each voltage conversion output block BK with the two levels of gradation voltages Vr 1 and Vr 256 based on the power potential VDD and the ground potential VSS.

In the power save mode, as shown in FIG. 5 , both of a switch SW 1 , which connects between an output terminal of the amplifier APa and the output terminal Y 1 in an on state, and a switch SW 2 , which connects between an output terminal of the amplifier APb and the output terminal Y 2 in an on state, are turned off in the output selector SEL. Furthermore, in the output selector SEL, both of a switch SW 3 , which connects between an output terminal of the amplifier APc and the output terminal Y 3 in an on state, and a switch SW 4 , which connects between an output terminal of the amplifier APd and the output terminal Y 4 in an on state, are turned off.

In the power save mode, as shown in FIG. 5 , both of a switch SWa, which connects between the output terminal of the amplifier APa and the output terminal Y 1 in an on state, and a switch SWb, which connects between the output terminal of the amplifier APa and the output terminal Y 2 in an on state, are turned on in the output selector SEL. Furthermore, both of a switch SWc, which connects between the output terminal of the amplifier APa and the output terminal Y 3 in the on state, and a switch SWd, which connects between the output terminal of the amplifier APa and the output terminal Y 4 in an on state, are turned on in the output selector SEL.

Therefore, as shown in FIG. 5 , the output selector SEL puts the output terminal of each of the amplifiers APb, APc, and APd in an open state.

In the state of the output selector SEL shown in FIG. 5 , the amplified gradation voltage Qa outputted from the amplifier APa is outputted through the switches SWa, SWb, SWc, and SWd and the output terminals Y 1 to Y 4 , as shown in FIG. 5 . In the power save mode, as described above, the amplified gradation voltage Qa has the gradation voltage Vr 1 corresponding to a minimum luminance (black) or the gradation voltage Vr 256 corresponding to a maximum luminance. Therefore, the amplified gradation voltage Qa that represents the two gradations of luminance is outputted from each of the output terminals Y 1 to Y 4 , using the gradation voltages Vr 1 and Vr 256 .

In an example shown in FIG. 5 , the amplified gradation voltage Qa that represents the luminance level of the pixel data P 1 by the two gradations is outputted as the drive voltages G 1 to G 4 . Therefore, the display device 20 performs monochromatic black and white display in the power save mode.

As described above, in the power save mode, the operation of the green gradation voltage generation circuit GVG and the blue gradation voltage generation circuit GVB is stopped in the drive voltage output part 132 , and the drive voltage output part 132 performs the monochromatic black and white display using the two gradations of gradation voltages Vr 1 and Vr 256 generated by the red gradation voltage generation circuit GVR.

Therefore, in the power save mode, the electric power consumption of the green gradation voltage generation circuit GVG and the blue gradation voltage generation circuit GVB becomes substantially zero.

Furthermore, in the power save mode, the output terminals of the three amplifiers APb, APc, and APd out of the four amplifiers APa to APd contained in each voltage conversion output block BK are put into the open state. Therefore, since an output current from each of the amplifiers APb, APc, and APd becomes zero, an output current from the whole n amplifiers AP is significantly reduced.

As described above, in the power save mode, two of the three gradation voltage generation circuits (GVR, GVG, and GVB) in the drive voltage output part 132 are stopped. Furthermore, since the output terminals of ¾ amplifiers (APb, APc, and APd) of each of the n amplifiers AP provided corresponding to the drive voltages G 1 to Gn are open, the electric power consumption in the power save mode is significantly reduced.

In the above-described embodiment, the monochromatic black and white display is performed in the power save mode, but monochromatic color display may be performed instead.

In the monochromatic color display, the output selector SEL included in the voltage conversion output part CVP of the configuration shown in FIGS. 2 to 4 is exchanged for an output selector SELa shown in FIG. 6 . Furthermore, as shown in FIG. 6 , voltage holding capacitors Ca, Cb, Cc, and Cd are connected to output terminals Y 1 to Y 4 of the output selector SELa, respectively.

FIG. 6 excerpts a voltage conversion output block BK that outputs drive voltages G 1 to G 4 , out of a plurality of voltage conversion output blocks BK.

As shown in FIG. 6 , the output selector SELa includes switches SW 1 to SW 4 and SWa to SWd, as in the case of the output selector SEL. In the normal mode, the operation of the output selector SELa is the same as that of the output selector SEL.

However, in the power save mode, the output selector SELa sequentially turns on the switches SWa, SWb, SWc, and SWd one-by-one in each horizontal scan period in accordance with a time chart shown in FIG. 7 , while keeping the switches SW 1 to SW 4 in an off state.

In other words, in a first cycle CYC 1 shown in FIG. 7 , the output selector SELa first turns on only the switch SWa out of the switches SWa to SWd. In the first cycle CYC 1 , an amplified gradation voltage Qa having, for example, a gradation voltage Vr 256 is supplied.

Therefore, as shown in FIG. 8 , the amplified gradation voltage Qa having the gradation voltage Vr 256 corresponding to a maximum luminance is outputted as a drive voltage G 1 through the switch SWa and the output terminal Y 1 .

Next, in a second cycle CYC 2 shown in FIG. 7 , the output selector SELa turns on only the switch SWb out of the switches SWa to SWd. In the second cycle CYC 2 , the amplified gradation voltage Qa having, for example, a gradation voltage Vr 1 is supplied.

Therefore, as shown in FIG. 9 , the amplified gradation voltage Qa having the gradation voltage Vr 1 corresponding to a minimum luminance is outputted as a drive voltage G 2 through the switch SWb and the output terminal Y 2 .

Next, in a third cycle CYC 3 shown in FIG. 7 , the output selector SELa turns on only the switch SWc out of the switches SWa to SWd. In the third cycle CYC 3 , the amplified gradation voltage Qa having, for example, the gradation voltage Vr 256 is supplied.

Therefore, as shown in FIG. 10 , the amplified gradation voltage Qa having the gradation voltage Vr 256 corresponding to the maximum luminance is outputted as a drive voltage G 3 through the switch SWc and the output terminal Y 3 .

Next, in a fourth cycle CYC 4 shown in FIG. 7 , the output selector SELa turns on only the switch SWd out of the switches SWa to SWd. In the fourth cycle CYC 4 , the amplified gradation voltage Qa having, for example, the gradation voltage Vr 1 is supplied.

Therefore, as shown in FIG. 11 , the amplified gradation voltage Qa having the gradation voltage Vr 1 corresponding to the minimum luminance is outputted as a drive voltage G 4 through the switch SWd and the output terminal Y 4 .

Therefore, according to the operation shown in FIG. 7 , since each drive voltage can be independently set at one of the two gradation voltages Vr 1 and Vr 256 , the monochromatic color display of red, green, blue, or a combination color of at least two of the three colors can be performed.

The aforementioned embodiment describes the case of adopting the organic EL panel as the display device 20 , but a liquid crystal display panel may be adopted instead of the organic EL panel. When the liquid crystal display panel is adopted as the display device 20 , for example, one pixel is constituted of three display cells (a red display cell, a green display cell, and a blue display cell). Accordingly, for example, as the output selector SEL or SELa, a selector including switches SWa to SWc and SW 1 to SW 3 shown in FIG. 5 is adopted. At this time, in the normal mode, all of the switches SWa to SWc are put into an off state. On the other hand, in the power save mode, the switches SWa to SWc are under on-off control as shown in FIG. 5 or 7 .

In the aforementioned embodiment, the red gradation voltage generation circuit GVR, the green gradation voltage generation circuit GVG, and the blue gradation voltage generation circuit GVB are used as the gradation voltage generation circuits, but the number of the gradation voltage generation circuits is not limited to 3, but may be 2 or 4 or more.

According to the aforementioned embodiment, in the power save mode, GVG and GVB out of the red gradation voltage generation circuit GVR, the green gradation voltage generation circuit GVG, and the blue gradation voltage generation circuit GVB are put into the stop state. However, GVR and GVB, or GVR and GVG may be put into the stop state.

In the aforementioned embodiment, the operation of the output selector SEL or SELa in the power save mode is described by taking a case where the one pixel is constituted of the four display cells (organic EL panel) or the three display cells (liquid display panel) as an example, but the number of display cells constituting one pixel is not limited to three or four. In other words, when one pixel is constituted of a k number (k is an integer less than n) of display cells, in the power save mode, the output selector SEL or SELa may output one amplified gradation voltage selected from k amplified gradation voltages, as a drive voltage, from k output terminals, in each of divisions into which the n amplified gradation voltages are divided into groups each containing k amplified gradation voltages.

In short, any driver including the following plurality of gradation voltage generation circuits, first to n-th DA converter circuits, first to n-th amplifiers, and output selector can be used as the data driver 13 .

In other words, each of the gradation voltage generation circuits (GVR, GVG, and GVB) generates the plurality of gradation voltages (Vr 1 to Vr 256 , Vg 1 to Vg 256 , or Vb 1 to Vb 256 ). Each of the first to n-th DA converter circuits (DC) is connected to one of the plurality of gradation voltage generation circuits, and selects and outputs the gradation voltage (U) corresponding to the luminance level represented by the pixel data (P), out of the plurality of gradation voltages generated by the connected gradation voltage generation circuit. The first to n-th amplifiers (AP) independently amplify the n gradation voltages outputted from the first to n-th DA converters, and output the n amplified gradation voltages (Q). The output selector (SEL or SELa) receives the mode signal (MOD) representing the normal mode or the power save mode. When the mode signal represents the normal mode, the n amplified gradation voltages are outputted from the n output terminals (Y), respectively.

The plurality of gradation voltage generation circuits receive the mode signal (MOD). When the mode signal indicates the power save mode, one gradation voltage generation circuit (GVR) out of the plurality of gradation voltage generation circuits generates the plurality of gradation voltages (Vr 1 and Vr 256 ). When the mode signal indicates the power save mode, the other gradation voltage generation circuits (GVG and GVB), except for the one gradation voltage generation circuit, stop generating the gradation voltages. When the mode signal indicates the power save mode, the output selector outputs one amplified gradation voltage (Qa) out of the k amplified gradation voltages from the k output terminals (Y 1 to Y 4 ) for each division (BK) into which the n amplified gradation voltages are divided into groups each containing k amplified gradation voltages. Furthermore, the output selector opens the output terminal of each of the amplifiers (APb to APd), except for the amplifier (APa) for generating one amplified gradation voltage (Qa), out of the k amplifiers (APa to APd) for generating the k amplified gradation voltages.

It is understood that the foregoing description and accompanying drawings set forth the preferred embodiments of the present invention at the present time. Various modifications, additions and alternative designs will, of course, become apparent to those skilled in the art in light of the foregoing teachings without departing from the spirit and scope of the disclosed invention. Thus, it should be appreciated that the present invention is not limited to the disclosed Examples but may be practiced within the full scope of the appended claims. This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2017-227646 filed on Nov. 28, 2017, the entire contents of which are incorporated herein by reference.