Shift-buffer circuit, gate driving circuit, display panel and driving method

The shift-buffer circuit according to claim 3 , wherein: the shift input circuit comprises a first shift transistor, a first electrode of the first shift transistor being connected with the shift input terminal, a gate electrode of the first shift transistor being connected with the shift input terminal, and a second electrode of the first shift transistor being connected with the shift pull-up node; the first shift reset circuit comprises a second shift transistor, a first electrode of the second shift transistor being connected with the shift pull-up node, a gate electrode of the second shift transistor being connected with the first shift pull-down node, and a second electrode of the second shift transistor being connected with the first power supply terminal; the shift output circuit comprises a third shift transistor, a first electrode of the third shift transistor being connected with the shift clock signal terminal, a gate electrode of the third shift transistor being connected with the shift pull-up node, and a second electrode of the third shift transistor being connected with the shift output terminal; the first shift output pull-down circuit comprises a fourth shift transistor, a first electrode of the fourth shift transistor being connected with the shift output terminal, a gate electrode of the fourth shift transistor being connected with the first shift pull-down node, and a second electrode of the fourth shift transistor being connected with the first power supply terminal; the first pull-down node control circuit comprises a fifth shift transistor and a sixth shift transistor, a first electrode of the fifth shift transistor being connected with the first power signal terminal, a gate electrode of the fifth transistor being connected with the first power signal terminal, a second electrode of the fifth shift transistor being connected with the first shift pull-down node, a first electrode of the sixth shift transistor being connected with the first shift pull-down node, a gate electrode of the sixth shift transistor being connected with the shift pull-up node, and a second electrode of the sixth shift transistor being connected with the first power supply terminal; and a first terminal of the shift storage capacitor is connected with the shift pull-up node, and a second terminal of the shift storage capacitor is connected with the shift output terminal.

The shift-buffer circuit according to claim 3 , wherein: the buffer input circuit comprises a first buffer transistor, a first electrode of the first buffer transistor being connected with the buffer input terminal, a gate electrode of the first buffer transistor being connected with an enabled signal terminal, and a second electrode of the first buffer transistor being connected with the buffer pull-up node; the first buffer reset circuit comprises a second buffer transistor, a first electrode of the second buffer transistor being connected with the buffer pull-up node, a gate electrode of the second buffer transistor being connected with the first buffer pull-down node, and a second electrode of the second buffer transistor being connected with the second power supply terminal; the buffer output circuit comprises a third buffer transistor, a first electrode of the third buffer transistor being connected with the buffer clock signal terminal, a gate electrode of the third buffer transistor being connected with the buffer pull-up node, and a second electrode of the third buffer transistor being connected with the buffer output terminal; the first buffer output pull-down circuit comprises a fourth buffer transistor, a first electrode of the fourth buffer transistor being connected with the buffer output terminal, a gate electrode of the fourth buffer transistor being connected with the first buffer pull-down node, and a second electrode of the fourth buffer transistor being connected with the second power supply terminal; and a first terminal of the buffer storage capacitor is connected with the buffer pull-up node, and a second terminal of the buffer storage capacitor is connected with the buffer output terminal.

The shift-buffer circuit according to claim 3 , wherein: the shift register further comprises: a second shift reset circuit, connected with the shift pull-up node, a second shift pull-down node and a first power supply terminal respectively; a second shift output pull-down circuit, connected with the shift output terminal, the second shift pull-down node and the first power supply terminal respectively; and a second pull-down node control circuit, connected with the second shift pull-down node, a second power signal terminal and the first power supply terminal respectively; and each of the buffers further comprises: a second buffer reset circuit, connected with the buffer pull-up node, a second buffer pull-down node and the second power supply terminal respectively; and a second buffer output pull-down circuit, connected with the buffer output terminal, the second buffer pull-down node and the second power supply terminal respectively, wherein a first power signal provided by the first power signal terminal and a second power signal provided by the second power signal terminal are mutually reverse signals.

The shift-buffer circuit according to claim 8 , wherein: the second shift reset circuit comprises a seventh shift transistor, a first electrode of the seventh shift transistor being connected with the shift pull-up node, a gate electrode of the seventh shift transistor being connected with the second shift pull-down node, and a second electrode of the seventh shift transistor being connected with the first power supply terminal; the second shift output pull-down circuit comprises an eighth shift transistor, a first electrode of the eighth shift transistor being connected with the shift output terminal, a gate electrode of the eighth shift transistor being connected with the second shift pull-down node, and a second electrode of the eighth shift transistor being connected with the first power supply terminal; the second pull-down node control circuit comprises a ninth shift transistor and a tenth shift transistor, a first electrode of the ninth shift transistor being connected with the second power signal terminal, a gate electrode of the ninth shift transistor being connected with the second power signal terminal, a second electrode of the ninth shift transistor being connected with the second shift pull-down node, a first electrode of the tenth shift transistor being connected with the second shift pull-down node, a gate electrode of the tenth shift transistor being connected with the shift pull-up node, and a second electrode of the tenth shift transistor being connected with the first power supply terminal; the second buffer reset circuit comprises a fifth buffer transistor, a first electrode of the fifth buffer transistor being connected with the buffer pull-up node, a gate electrode of the fifth buffer transistor being connected with the second buffer pull-down node, and a second electrode of the fifth buffer transistor being connected with the second power supply terminal; and the second buffer output pull-down circuit comprises a sixth buffer transistor, a first electrode of the sixth buffer transistor being connected with the buffer output terminal, a gate electrode of the sixth buffer transistor being connected with the second buffer pull-down node, and a second electrode of the sixth buffer transistor being connected with the second power supply terminal.

The shift-buffer circuit according to claim 8 , wherein the second buffer pull-down node is connected with the second shift pull-down node.

The gate driving circuit according to claim 14 , wherein: an enabled signal terminal of a buffer in the shift-buffer circuit of the (2n−1)-th stage is configured to receive a first enabled signal; and an enabled signal terminal of a buffer in the shift-buffer circuit of the 2n-th stage is configured to receive a second enabled signal.

A display device, comprising the display panel according to claim 16 .