US Patent 10,381,993 — Single controller automatic calibrating circuits for reducing or canceling offset voltages in operational amplifiers in an instrumentation amplifier

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Abstract

Single controller automatic calibrating circuits for reducing or canceling offset voltages in operational amplifiers (op-amps) in an instrumentation amplifier are disclosed. An automatic calibrating op-amp system is provided that includes an instrumentation amplifier, which includes a front-end amplifier circuit comprising at least one front-end op-amp and a final-stage amplifier circuit comprising a final-stage op-amp. The op-amp(s) can include auxiliary differential inputs for offset voltage cancellation. The automatic calibrating op-amp system also includes an automatic calibration circuit employing a single controller to generate calibration signals on a calibration output to an auxiliary differential input(s) of an op-amp(s) in the instrumentation amplifier for offset voltage cancellation. The automatic calibration circuit includes a single controller to generate calibration signals to the instrumentation amplifier to reduce or cancel offset voltage, thereby eliminating the need to provide multiple automatic calibration circuits or an automatic calibration circuit employing multiple controllers.

Claims

30 · 4 independent · depth 4

30 granted claims

›1.independentAn instrumentation amplifier, comprising: a gain resistor circuit coupled between a first resistor circuit node and a second resistor circuit node; a …+9

An instrumentation amplifier, comprising: a gain resistor circuit coupled between a first resistor circuit node and a second resistor circuit node; a front-end amplifier circuit comprising: a first front-end operational amplifier (op-amp), comprising: a first front-end voltage input configured to receive a first input voltage on a first voltage input, and a second front-end voltage input coupled to the first resistor circuit node; a first front-end auxiliary differential input pair comprising a first front-end auxiliary differential input coupled to a first calibration input configured to receive a first calibration signal from a calibration circuit, and a second front-end auxiliary differential input coupled to a second calibration input configured to receive a second calibration signal from the calibration circuit; and a first front-end voltage output; the first front-end op-amp configured to generate a first intermediate output voltage on the first front-end voltage output based on the first input voltage and a voltage at the second front-end voltage input, and a first front-end offset voltage based on the first calibration signal applied to the first front-end auxiliary differential input and the second calibration signal applied to the second front-end auxiliary differential input; a second front-end op-amp, comprising: a third front-end voltage input configured to receive a second input voltage on a second voltage input, and a fourth front-end voltage input coupled to the second resistor circuit node; a second front-end auxiliary differential input pair comprising a third front-end auxiliary differential input coupled to the second calibration input, and a fourth front-end auxiliary differential input coupled to the first calibration input; and a second front-end voltage output; the second front-end op-amp configured to generate a second intermediate output voltage on the second front-end voltage output based on the second input voltage, and a voltage at the fourth front-end voltage input and a second front-end offset voltage based on the first calibration signal applied to the fourth front-end auxiliary differential input and the second calibration signal applied to the third front-end auxiliary differential input; and a final-stage amplifier circuit comprising a final-stage op-amp, comprising: a first final-stage voltage input configured to receive a first input voltage, and a second final-stage voltage input coupled to the first resistor circuit node; and a final-stage voltage output; the final-stage op-amp configured to generate a final-stage output voltage on the final-stage voltage output based on the first intermediate output voltage and the second intermediate output voltage.

›2.↳ 1The instrumentation amplifier of claim 1 , further comprising: a first resistor circuit coupled between the first front-end voltage output and the fir…d2+1

›4.↳ 1The instrumentation amplifier of claim 1 , further comprising: a third resistor circuit coupled between the first final-stage voltage input and the fi…d2+1

›6.↳ 1The instrumentation amplifier of claim 1 , further comprising a switch network circuit coupled to the first front-end voltage input and the second fro…d2+2

›9.↳ 1The instrumentation amplifier of claim 1 integrated into an integrated circuit (IC).d2

›10.↳ 1The instrumentation amplifier of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navig…d2

›11.independentAn automatic calibrating operational amplifier (op-amp) system, comprising: an instrumentation amplifier, comprising: at least one front-end amplifier…+14

An automatic calibrating operational amplifier (op-amp) system, comprising: an instrumentation amplifier, comprising: at least one front-end amplifier circuit, comprising: a first front-end voltage input configured to receive a first input voltage on a first voltage input; a second front-end voltage input configured to receive a second input voltage on a second voltage input; at least one front-end auxiliary differential input pair; and at least one front-end voltage output; the at least one front-end amplifier circuit configured to generate at least one intermediate output voltage on the at least one front-end voltage output based on the first input voltage and the second input voltage, and at least one front-end offset voltage based on a plurality of calibration signals applied to the at least one front-end auxiliary differential input pair; a final-stage amplifier circuit comprising a final-stage op-amp, comprising: a first final-stage voltage input configured to receive a first final-stage input voltage, and a second final-stage voltage input coupled to a first resistor circuit node; a final-stage auxiliary differential input pair; and a final-stage voltage output; the final-stage op-amp configured to generate a final-stage output voltage on the final-stage voltage output based on the at least one first intermediate output voltage, and a final-stage offset voltage applied to the final-stage auxiliary differential input pair; and an automatic calibration circuit coupled to the final-stage voltage output of the instrumentation amplifier, the automatic calibration circuit comprising: a single successive approximation register (SAR) controller configured to successively generate a plurality of bit signals in response to a calibration mode signal on a calibration mode input indicating a calibration mode, wherein a value of each successive plurality of bit signals is based on the final-stage output voltage at the final-stage voltage output; and a digital-to-analog converter (DAC) comprising a calibration output coupled to at least one of the at least one front-end auxiliary differential input pair comprising a first front-end auxiliary differential input pair and a second front-end auxiliary differential input pair, and the final-stage auxiliary differential input pair, the DAC configured to: convert each successive plurality of bit signals into a plurality of analog calibration signals on the calibration output based on the final-stage output voltage in response to the calibration mode signal indicating the calibration mode; and apply the plurality of analog calibration signals on the calibration output in response to the calibration mode signal indicating an amplify mode to compensate for a composite offset voltage of the instrumentation amplifier.

›12.↳ 11The automatic calibrating op-amp system of claim 11 , wherein: the at least one front-end amplifier circuit is configured to generate the at least one…d2

›13.↳ 11The automatic calibrating op-amp system of claim 11 , wherein: the at least one front-end amplifier circuit comprises: a first front-end op-amp, compr…d2

The automatic calibrating op-amp system of claim 11 , wherein: the at least one front-end amplifier circuit comprises: a first front-end op-amp, comprising: a first front-end voltage input configured to receive the first input voltage and a second front-end input voltage; and a first front-end auxiliary differential input pair comprising a first front-end auxiliary differential input coupled to a first calibration input configured to receive a first calibration signal among the plurality of calibration signals, and a second front-end auxiliary differential input coupled to a second calibration input configured to receive a second calibration signal among the plurality of calibration signals; a first front-end voltage output; the first front-end op-amp configured to generate a first intermediate output voltage on the first front-end voltage output based on the first input voltage and a voltage at the second front-end voltage input, and a first front-end offset voltage based on the first calibration signal applied to the first front-end auxiliary differential input and the second calibration signal applied to the second front-end auxiliary differential input; and a second front-end op-amp, comprising: a third front-end voltage input configured to receive the second input voltage, and a fourth front-end voltage input; a second front-end auxiliary differential input pair comprising a third front-end auxiliary differential input coupled to the second calibration input and a fourth front-end auxiliary differential input coupled to the first calibration input; and a second front-end voltage output; the second front-end op-amp configured to generate a second intermediate output voltage on the second front-end voltage output based on the second input voltage and a voltage at the fourth front-end voltage input, and a second front-end offset voltage based on the first calibration signal applied to the fourth front-end auxiliary differential input and the second calibration signal applied to the third front-end auxiliary differential input; the final-stage amplifier circuit comprises a final-stage op-amp, comprising: the first final-stage voltage input configured to receive the first input voltage and the second final-stage voltage input; and the final-stage voltage output; the final-stage op-amp configured to generate the final-stage output voltage on the final-stage voltage output based on the first intermediate output voltage and the second intermediate output voltage; and the DAC comprises the calibration output coupled to the first front-end auxiliary differential input pair and the second front-end auxiliary differential input pair.

›14.↳ 11The automatic calibrating op-amp system of claim 11 , wherein: the DAC comprises the calibration output coupled to the final-stage auxiliary different…d2

›15.↳ 11The automatic calibrating op-amp system of claim 11 , wherein: the at least one front-end amplifier circuit comprises: a first front-end op-amp, compr…d2

›16.↳ 11The automatic calibrating op-amp system of claim 11 , further comprising a switchable bias voltage circuit comprising: a bias voltage input coupled to…d2+2

›17.↳ 16The automatic calibrating op-amp system of claim 16 , wherein: in response to the calibration mode signal on the calibration mode input indicating the…d3+1

›19.↳ 11The automatic calibrating op-amp system of claim 11 , wherein the single SAR controller comprises: a voltage compare input configured to receive an op…d2+3

›20.↳ 19The automatic calibrating op-amp system of claim 19 , wherein the DAC comprises the plurality of bit signal inputs configured to receive the successiv…d3

›21.↳ 19The automatic calibrating op-amp system of claim 19 , wherein the automatic calibration circuit further comprises: a first switch configured to be act…d3+1

›23.↳ 11The automatic calibrating op-amp system of claim 11 , wherein the DAC is further configured to: receive a top reference voltage; receive a bottom refe…d2

›24.↳ 11The automatic calibrating op-amp system of claim 11 integrated into an integrated circuit (IC).d2

›25.↳ 11The automatic calibrating op-amp system of claim 11 integrated into a device selected from the group consisting of: a set top box; an entertainment un…d2

›26.independentAn automatic calibrating operational amplifier (op-amp) system, comprising: a means for generating at least one intermediate output voltage on at leas…

›27.independentA method of automatically calibrating an offset voltage in an instrumentation amplifier, comprising: generating at least one intermediate output volta…+3

›28.↳ 27The method of claim 27 , wherein: generating the at least one intermediate output voltage on the at least one front-end voltage output comprises: gene…d2

›29.↳ 27The method of claim 27 , wherein: generating the final-stage output voltage on the final-stage voltage output comprises generating the final-stage out…d2

›30.↳ 27The method of claim 27 , wherein: generating the at least one intermediate output voltage on the at least one front-end voltage output comprises: gene…d2

Classifications

2 codes

IPC · International Patent Classification

Section H — Electricity

H03F1/02
H03F3/45

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384 days filing → grant

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Examiner

Henry Choe

art unit 2842 · TC 2800

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1 priority documents

Priority

20 Apr 2018

earliest claimed

›Priority documents — 1

Type	Document	Date
provisional	US 62660432	20 Apr 2018

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