A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Claims

14 · 1 independent · depth 5

14 granted claims

›1.independentA semiconductor device comprising: an interface chip, a first memory chip including a first interconnect which extends from a back surface side to a t…+13

›2.↳ 1The device according to claim 1 , wherein the first FIFO receives the data of a plurality of bits from the first memory chip, the second FIFO includes…d2+9

›3.↳ 2The device according to claim 2 , wherein in the interface chip, at least part of the second FIFOs are provided along a first direction, at least anot…d3+4

›9.↳ 2The device according to claim 2 , wherein the first FIFO receives the data from the first memory chip and outputs the data in synchronism with a first…d3+2

›12.↳ 2The device according to claim 2 , further comprising a second memory chip including a second interconnect which extends from a back surface side to a …d3

›8.↳ 1The device according to claim 1 , further comprising a first bump provided on the top surface side of the first memory chip to be electrically connect…d2

›13.↳ 1The device according to claim 1 , wherein a bus width between the first memory chip and the interface chip is the same as a bus width of the first FIF…d2

›14.↳ 1The semiconductor device according to claim 1 , wherein the first memory chip includes a memory circuit which outputs the data.d2

Classifications

10 codes

IPC · International Patent Classification

Section G — Physics

G11C16/04
G11C16/10
G06F5/06
G11C16/32
G11C7/10
G11C16/12
G11C7/02
G11C16/26
G11C16/16
G06F13/16

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Pendency

1.2 y

424 days filing → grant

Office actions

non-final + final

Responses

no RCE

Examiner

Pho M Luu

art unit 2824 · TC 2800

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Citations: 36 back · 0 forward

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Priority chain

2 priority documents

Priority

28 May 2015

earliest claimed

›Priority documents — 2

Type	Document	Date
provisional	US 62167703	28 May 2015
related publication	US 20180294038 A1	11 Oct 2018

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