Tank circuit and frequency hopping for isolators

The present disclosure generally relates to circuits for transmitting power across an isolation barrier and applying frequency hopping for power transmission.

Some integrated circuits include two or more voltage domains that are galvanically isolated from one another. In such integrated circuits, it may be desirable to transmit power from one domain to another. Existing circuits to transmit power from one domain to another, while maintaining galvanic isolation, suffer from a variety of drawbacks. For example, some conventional tank circuits use cross-coupled metal oxide semiconductor (MOS) transistors, which lead to poor efficiency and poor electromagnetic interference (EMI) performance.

Therefore, the inventors recognized a need in the art for circuits and methods to efficiently transmit power between galvanically-isolated domains and improve EMI performance.

FIG. 1 illustrates an oscillator circuit according to an embodiment of the present disclosure.

FIG. 2 illustrates an oscillator circuit according to an embodiment of the present disclosure.

FIG. 3 illustrates a frequency hopping control method according to an embodiment of the present disclosure.

FIG. 4 illustrates an exemplary frequency hopping diagram according to an embodiment of the present disclosure.

FIG. 5 illustrates a topology for an integrated circuit according to an embodiment of the present disclosure.

Embodiments of the present disclosure may provide a circuit comprising a tank circuit. The tank circuit may include an inductor having a pair of terminals, a first pair of transistors, and a first pair of capacitors. Each transistor may be coupled between a respective terminal of the inductor and a reference voltage along a source-to-drain path of the transistor. Each capacitor may be provided in a signal path between an inductor terminal coupled to a respective first transistor in the first pair and a gate of a second transistor in the first pair.

Embodiments of the present disclosure may provide controller method for generating an oscillation frequency. The method may include at a first time instance: activating a first pair of transistors of the tank circuit, each coupled between a respective terminal of an inductor having a pair of terminals and a reference voltage along a source-to-drain path of the transistor; coupling, as a result of the activating, a first of a pair of capacitors of the tank circuit provided in a signal path between a source or drain terminal of a first transistor in the first pair and a gate of a second transistor in the first pair; and coupling, as a result of the activating, a second of the pair of capacitors provided in a signal path between a source or drain terminal of the second transistor in the first pair and a gate of the first transistor in the first pair, wherein a voltage having an oscillation frequency is generated at the terminals of the inductor to transmit power over an isolation barrier.

Embodiments of the present disclosure may provide a circuit. The circuit may include a means for activating a first pair of transistors of an inductor-capacitor (LC) tank at a first time instance, each transistor coupled between a respective terminal of an inductor having a pair of terminals and a reference voltage along a source-to-drain path of the transistor. The circuit may also include a first means for coupling, as a result of the activating, a first of a pair of capacitors of the tank circuit provided in a signal path between a source or drain terminal of a first transistor in the first pair and a gate of a second transistor in the first pair. The circuit may further include a second means coupling, as a result of the activating, a second of the pair of capacitors provided in a signal path between a source or drain terminal of the other transistor in the first pair and a gate of the first transistor in the first pair, wherein a voltage having the oscillation frequency is generated at the terminals of the inductor to transmit power over an isolation barrier.

FIG. 1 illustrates an oscillator circuit 100 according to an embodiment of the present disclosure. The oscillator circuit 100 may include an LC tank 110 controlled by a controller 120 . The LC tank 110 may include a pair of inductors L 1 . 1 , L 1 . 2 , a pair of capacitors C 0 . 1 , C 0 . 2 , a pair of double-diffused metal oxide semiconductor (DMOS) transistors D 0 . 1 , D 0 . 2 , and a pair of disabling transistors T D 0 . 1 , T D 0 . 2 .

The pair of inductors L 1 . 1 , L 1 . 2 may be coupled in series to form a center tap and a pair of terminals (V N , V P ). The center tap may be coupled to a power source VDD. The pair of DMOS transistors D 0 . 1 , D 0 . 2 may each be coupled, along a respective source-to-drain path, between a respective terminal of the pair of inductors L 1 . 1 , L 1 . 2 and a reference voltage GND. The capacitor C 0 . 1 may be provided in a signal path between the inductor L 1 . 1 coupled to DMOS transistor D 0 . 1 and a gate of the DMOS transistor D 0 . 2 . Similarly, the capacitor C 0 . 2 may be provided in a signal path between the inductor L 1 . 2 coupled to DMOS transistor D 0 . 2 and a gate of the DMOS transistor D 0 . 1 . The pair of disabling transistors T D 0 . 1 , T D 0 . 2 may have their gates coupled to a control input (OFF) (logic high) and may be coupled, along their respective source-to-drain paths, between the gates of the DMOS transistors D 0 . 1 , D 0 . 2 , respectively, and the reference voltage GND. The disabling transistors T D 0 . 1 , T D 0 . 2 may be implemented as any known transistor type (e.g., MOS, FET, BJT, DMOS, etc.).

The controller 120 may provide a control signal OFF (logic high) to the gates of the disabling transistors T D 0 . 1 , T D 0 . 2 to activate the disabling transistors T 0 . 1 , T 0 . 2 . When activated, the disabling transistors T D 0 . 1 , T D 0 . 2 may pull the gates of the DMOS transistors D 0 . 1 , D 0 . 2 low, thereby turning off the DMOS transistors D 0 . 1 , D 0 . 2 and disabling the LC tank 210 . When the disabling transistors T D 0 . 1 , T D 0 . 2 are deactivated (i.e., no OFF signal), the DMOS transistors D 0 . 1 , D 0 . 2 may be activated, coupling the capacitors C 0 . 1 , C 0 . 2 to the inductors L 1 . 1 , L 1 . 2 , respectively. Consequently, the LC tank 110 may resonate or oscillate at a resonance or oscillation frequency fosc and transmit power from the power source VDD to a second voltage domain 130 via a pair of inductors L 2 . 1 , L 2 . 2 . An isolation barrier may be provided in between inductors L 1 . 1 , L 1 . 2 and inductors L 2 . 1 , L 2 . 2 ; therefore, the inductors L 2 . 1 , L 2 . 2 may be magnetically coupled to, but galvanically isolated from, the inductors L 1 . 1 , L 1 . 2 . In an embodiment, the inductors L 1 . 1 , L 1 . 2 may be the first winding of a transformer and the inductors L 2 . 1 , L 2 . 2 may the secondary winding of the transformer. A peak-to-peak voltage of an oscillation voltage of the LC tank 110 , between nodes V N and V P , may be two to three times the voltage of the power source VDD.

The oscillation frequency fosc of the oscillator circuit 100 may be related to the inductances of the inductors L 1 . 1 , L 1 . 2 , the capacitances of the capacitors C 0 . 1 , C 0 . 2 , and the capacitances of the DMOS transistors D 0 . 1 , D 0 . 2 . Therefore, the oscillation frequency fosc may be tuned by tuning the sizes of the inductors L 1 . 1 , L 1 . 2 , the capacitors C 0 . 1 , C 0 . 2 , and the DMOS transistors D 0 . 1 , D 0 . 2 during fabrication of the LC tank 110 . Ideally, the inductors L 1 . 1 , L 1 . 2 would have substantially the same inductances, the capacitors C 0 . 1 , C 0 . 2 would have substantially the same capacitances, and the DMOS transistors D 0 . 1 , D 0 . 2 would be sized to have substantially identical (parasitic) capacitances. In practice, however, due to manufacturing variations and other factors, the inductances and capacitances may not be perfectly matched. In one embodiment, the DMOS transistors D 0 . 1 , D 0 . 2 and the disabling transistors T D 0 . 1 , T D 0 . 2 may be fabricated as n-type transistors.

FIG. 2 illustrates an oscillator circuit 200 according to an embodiment of the present disclosure. The oscillator circuit 200 may include an LC tank 210 , a plurality of sub-tanks 240 . 1 - 240 .N, and a controller 220 . The LC tank 210 may include a pair of inductors L 1 . 1 , L 1 . 2 , a pair of capacitors C 0 . 1 , C 0 . 2 , a pair of DMOS transistors D 0 . 1 , D 0 . 2 , and a pair of disabling transistors T 0 . 1 , T 0 . 2 . Each sub-tank 240 . 1 - 240 .N may include a pair of capacitors C 1 . 1 , C 1 . 2 -CN. 1 , CN. 2 , a pair of DMOS transistors D 1 . 1 , D 1 . 2 -DN. 1 , DN. 2 , a pair of disabling transistors T D 1 . 1 , T D 1 . 2 -T D N. 1 , T D N. 2 , and a pair of enabling transistors T E 1 . 3 , T E 1 . 4 -T E N. 3 , T E N. 4 .

In the LC tank 210 , the pair of inductors L 1 . 1 , L 1 . 2 may be coupled in series to form a center tap and a pair of terminals. The center tap may be coupled to a power source VDD. The pair of DMOS transistors D 0 . 1 , D 0 . 2 may each be coupled, along a respective source-to-drain path, between a respective terminal of the pair of inductors L 1 . 1 , L 1 . 2 and a reference voltage GND. The capacitor C 0 . 1 may be provided in a signal path between the inductor L 1 . 1 coupled to DMOS transistor D 0 . 1 and a gate of the DMOS transistor D 0 . 2 . Similarly, the capacitor C 0 . 2 may be provided in a signal path between the inductor L 1 . 2 coupled to DMOS transistor D 0 . 2 and a gate of the DMOS transistor D 0 . 1 . The pair of disabling transistors T D 0 . 1 , T D 0 . 2 may have their gates coupled to a control input (OFF) and may be coupled, along their respective source-to-drain paths, between the gates of the DMOS transistors D 0 . 1 , D 0 . 2 , respectively, and the reference voltage GND.

As shown in FIG. 2 , each sub-tank 240 . 1 - 240 .N may be coupled in parallel with the LC tank 210 across the pair of terminals (V N , V P ) of the inductors L 1 . 1 , L 1 . 2 . In each sub-tank 240 . 1 - 240 .N, the pair of DMOS transistors D 1 . 1 , D 1 . 2 -DN. 1 , DN. 2 may each be coupled, along a respective source-to-drain path, between a respective terminal of the pair of inductors L 1 . 1 , L 1 . 2 and the reference voltage GND. The capacitor C 1 . 1 -CN. 1 may be provided in series with the enabling transistor T E 1 . 3 -T E N. 3 in a signal path between the inductor L 1 . 1 coupled to DMOS transistor D 1 . 1 -DN. 1 and a gate of the DMOS transistor D 1 . 2 -DN. 2 . Similarly, the capacitor C 1 . 2 -CN. 2 may be provided in series with the enabling transistor T E 1 . 4 -T E N. 4 in a signal path between the inductor L 1 . 2 coupled to DMOS transistor D 1 . 2 -DN. 2 and a gate of the DMOS transistor D 1 . 1 -DN. 1 . The enabling transistors T E 1 . 3 -T E N. 3 and T E 1 . 4 -T E N. 4 may have their gates coupled to respective control inputs (CTRL 1 . 1 -CTRLN. 1 ). The pair of disabling transistors T D 1 . 1 , T D 1 . 2 -T D N. 1 , T D N. 2 may have their gates coupled to another control input (CTRL 1 . 2 -CTRLN. 2 ), and may be coupled, along their respective source-to-drain paths, between the gates of the DMOS transistors D 1 . 1 , D 1 . 2 -DN. 1 , DN. 2 , respectively, and the reference voltage GND.

The controller 220 may provide control signals CTRL 1 . 2 -CTRLN. 2 (e.g., logic high) to the gates of the disabling transistors T D 0 . 1 , T D 0 . 2 -T D N. 1 , T D N. 2 to activate the disabling transistors T D 0 . 1 , T D 0 . 2 -T D N. 1 , T D N. 2 . The control signals CTRL 1 . 2 -CTRLN. 2 each may be formed by the controller as a logical OR of the control signal OFF and an inverted corresponding one of the control signals CTRL 1 . 1 -CTRLN. 1 . When activated, the disabling transistors T D 0 . 1 , T D 0 . 2 -T D N. 1 , T D N. 2 may pull the gates of the DMOS transistors D 0 . 1 , D 0 . 2 -DN. 1 , DN. 2 low, thereby turning off the DMOS transistors D 0 . 1 , D 0 . 2 -DN. 1 , DN. 2 and disabling the LC tank 210 and the sub-tanks 240 . 1 - 240 .N.

When the disabling transistors T D 0 . 1 , T D 0 . 2 -T D N. 1 , T D N. 2 are deactivated, the DMOS transistors D 0 . 1 , D 0 . 2 may be activated, placing the capacitors C 0 . 1 , C 0 . 2 in series with the inductors L 1 . 1 , L 1 . 2 , respectively. Consequently, the LC tank 210 may resonate or oscillate at a resonance or oscillation frequency fosc and transmit power from the power source VDD to a second voltage domain 230 via a pair of inductors L 2 . 1 , L 2 . 2 . The inductors L 2 . 1 , L 2 . 2 may be magnetically coupled to, but galvanically isolated from, the inductors L 1 . 1 , L 1 . 2 . The inductors L 1 . 1 , L 1 . 2 may be the first winding of a transformer and the inductors L 2 . 1 , L 2 . 2 may the secondary winding of the transformer.

When the disabling transistors T D 1 . 1 , T D 1 . 2 -T D N. 1 , T D N. 2 are deactivated, the controller 220 may also activate one or more of the sub-tanks 240 . 1 - 240 .N with control signals CTRL 1 . 1 -CTRLN. 1 , respectively. The controller 220 may provide the control signal CTRL 1 . 1 , . . . , CTRLN. 1 (e.g., logic high) to the gates of the enabling transistors T E 1 . 3 , T E 1 . 4 -TN. 3 , TN. 4 to enable the enabling transistors T E 1 . 3 , T E 1 . 4 -T E N. 3 , T E N. 4 . Consequently, the DMOS transistors D 1 . 1 , D 1 . 2 -DN. 1 , DN. 2 may be activated, placing the capacitor C 1 . 1 -CN. 1 in parallel with the capacitor C 0 . 1 , and the capacitor C 1 . 2 -CN. 2 in parallel with the capacitor C 0 . 2 , thereby increasing the effective capacitance of the oscillator circuit 200 and decreasing the oscillation frequency fosc. Therefore, the oscillation frequency fosc may be set to a plurality of discrete values based on the combination/permutation of the sub-tanks 240 . 1 - 240 .N activated by the controller 220 . The controller 220 may be programmed to “hop” from one oscillation frequency fosc to another at a predetermined time step tstep by selectively activating the sub-tanks 240 . 1 - 240 .N based on a predetermined oscillation frequency fosc sequence. The predetermined oscillation frequency fosc sequence may last for a time period T and may be repeated thereafter. The predetermined oscillation frequency fosc sequence may be in an ascending order, a descending order, a random order, or any other suitable order.

The oscillation frequency fosc, with the sub-tanks 240 . 1 - 240 .N deactivated, may be tuned by tuning the sizes of the inductors L 1 . 1 , L 1 . 2 , the capacitors C 0 . 1 , C 0 . 2 , and the DMOS transistors D 0 . 1 , D 0 . 2 during fabrication of the LC tank 210 . Ideally, the inductors L 1 . 1 , L 1 . 2 would have substantially identical inductances, the capacitors C 0 . 1 , C 0 . 2 would have substantially identical capacitances, the DMOS transistors D 0 . 1 , D 0 . 2 would be sized to have substantially identical capacitances. In practice, however, due to manufacturing variations and other factors, the inductances and capacitances may not be perfectly matched. In one embodiment, the DMOS transistors D 0 . 1 , D 0 . 2 -DN. 1 , DN. 2 , the disabling transistors T D 0 . 1 , T D 0 . 2 -T D N. 1 , T D N. 2 , and the enabling transistors T E 1 . 3 , T E 1 . 4 -T E N. 3 , T E N. 4 may be fabricated as n-type transistors.

The sub-tanks 240 . 1 - 240 .N may be fabricated to be identical such that, when activated, each sub-tank 240 . 1 , . . . , 240 .N may decrease the oscillation frequency fosc by a frequency step fstep. The frequency step fstep may be tuned by tuning the sizes of capacitors C 1 . 1 , C 1 . 2 -CN. 1 , CN. 2 and the DMOS transistors D 1 . 1 , D 1 . 2 -DN. 1 , DN. 2 . Ideally, the capacitors C 1 . 1 , C 1 . 2 -CN. 1 , CN. 2 would have substantially identical capacitances and the DMOS transistors D 1 . 1 , D 1 . 2 -DN. 1 , DN. 2 would be sized to have substantially identical capacitances. In practice, however, due to manufacturing variations and other factors, the capacitances may not be perfectly matched. The time step tstep, the time period T, and the frequency step fstep may be set based on the application of the oscillator circuit 200 and the electromagnetic interference (EMI) requirements, for example. Further, the number of sub-tank circuits may correspond to the number of bits in the frequency hopping scheme. For example, for a 4 bit frequency hopping scheme, 15 sub-tank circuits (2 4 −1) may be provided. The 15 sub-tank circuits and the LC tank circuit may provide 16 carriers for the 4 bit frequency hopping scheme.

FIG. 3 illustrates a frequency “hopping” control method 300 according to an embodiment of the present disclosure. The method 300 may be performed by the oscillator circuit 200 of FIG. 2 , for example. The method 300 starts at step 310 and, at step 320 , a predetermined oscillation frequency fosc sequence {(t 0 , f 0 ), (t 1 , f 1 ), . . . , (tN, fN)} may be loaded. The predetermined oscillation frequency fosc sequence may be in an ascending order, a descending order, a random order, or any other suitable order. The predetermined oscillation frequency fosc sequence may define different oscillation frequencies at different times. At step 330 , the time is t 0 ; therefore, select sub-tanks may be activated (i.e., turned or kept on) to generate the corresponding oscillation frequency fosc=f 0 . At step 340 , the time is t 1 ; therefore, select sub-tanks may be activated (i.e., turned or kept on) to generate the corresponding oscillation frequency fosc=f 1 . At step 350 , the time is t 2 ; therefore, select sub-tanks may be activated (i.e., turned or kept on) to generate the corresponding oscillation frequency fosc=f 2 . The method may continue until the end of the time period T at tN, where select sub-tanks may be activated (i.e., turned or kept on) to generate the corresponding oscillation frequency fosc=fN at step 360 . Thereafter, the frequency hopping steps (i.e, steps 330 - 360 ) may be repeated for the subsequent time periods T.

FIG. 4 illustrates an exemplary frequency hopping diagram 400 according to an embodiment of the present disclosure. The diagram 400 illustrates how an oscillation frequency fosc of an oscillator circuit (e.g., the oscillator circuit 200 ) may be changed at a time step tstep to follow a predetermined oscillation frequency fosc sequence {(t 0 , f 0 ), (t 1 , f 1 ), . . . , (tN, fN)} over a time period T (e.g., by the controller 220 employing the method 300 of FIG. 3 ). The predetermined oscillation frequency fosc sequence in this example is in a random order. However, as discussed, the predetermined oscillation frequency fosc sequence may also be set to be in an ascending order, a descending order, a random order, or any other suitable order.

FIG. 5 illustrates a topology for an integrated circuit 500 according to an embodiment of the present disclosure. The integrated circuit 500 may include a first die 502 and a second die 504 . The first die 502 may include an LC tank 510 and a plurality of sub-tanks 540 . 1 - 540 .N connected in parallel with the LC tank 510 , and a secondary inductor 550 . The LC tank 510 may include a primary inductor 512 fabricated to be adjacent to the secondary inductor 550 such that the primary inductor 512 may be magnetically coupled to, but galvanically isolated from, the secondary inductor 550 . The secondary inductor 550 may be coupled to the second die 540 , via bonding wires for example.

The LC tank 510 and the sub-tanks 540 . 1 - 540 .N may correspond respectively to the LC tank 210 and the sub-tanks 240 . 1 - 240 .N of FIG. 2 . The primary inductor 512 may correspond to the pair of inductors L 1 . 1 , L 1 . 2 and the secondary inductor 550 to the pair of inductors L 2 . 1 , L 2 . 2 . Thus, with the layout shown in FIG. 5 , the integrated circuit 500 may transmit power from the first die 502 (i.e., a first voltage domain) to the second die 504 (i.e., a second voltage domain via the secondary inductor 550 ).

Several embodiments of the disclosure are specifically illustrated and/or described herein. However, it will be appreciated that modifications and variations of the disclosure are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the disclosure. Further variations are permissible that are consistent with the principles described above.